Errata on PLL for LPC551x

[yamakatb]

Hello,

Errata sheet LPC55S1x/LPC551x question about 3.12 PLL.1: PLL LOCK bit is not reliable.

On the LPC55S1x/LPC551x, the PLL status LOCK bit is not always reliable in the ranges specified and as a result, the PLL doesn´t initialize correctly.

Does this mean that PLLxSTAT_LOCK may not be set to 1 even after PLL stabilization?
Older SDKs loop until this bit is set to 1.
I am using Fref=16MHz.
Does this mean that if I don't update my software I could get an infinite loop due to this?

Best Regards,

[xiangjun_rong]

Hi,

The errata description about PLL is confused, for LPC551x,I suppose that when the Fref ranges from 100K to 20Mhz, the LOCK bit can be set reliably, you are not required to add delay. If the Fref is greater than 20MHz or less than 100Khz, the LOCK bit in status register is not reliable, the delay is required.

Anyway, I will contact AE team for confirmation.

BR

XiangJun Rong

[yamakatb]

Hi @xiangjun_rong  ,

I see this as an interpretation.
For Fref < 100 kHz  20 MHz:.
- If the PLL lock detector status bit is 1 before the wait time duration ((500us +
400/Fref)) is completed, the PLL is stable.
- If the PLL lock detector status bit is 0 but the wait time duration ((500us + 400/Fref)) is
If the PLL lock detector status bit is 0 but the wait time duration ((500us + 400/Fref) is completed, the PLL is stable.
Software workaround is implemented in SDK 2.14 clock driver version 2.3.7.

Thank you for the confirmation. Waiting for further report.

Best regards,

[xiangjun_rong · Accepted solution]

Hi,

This is AE reply:

"Hello, yes in some specific scenario bit is not set even after PLL stabilization. That is why new SW is recommended to be used.   

"

Hope it can help you

BR

XiangJun Rong