EMC and addressing

[lpcware]

Content originally posted in LPCWare by tjoAG on Wed May 30 06:49:32 MST 2012
Hi all

I'm currently trying to get our SDRAM interface up running. It is a custom board running a LPC1788 at 120 MHz with a Micron MT48LC8M16A2 (128 Mbit, 8M*16, B=4, R=12, C=9)

In the user manual for the lpc1788 UM10470 page 179 it is stated:

"The SDRAM bank select pins BA1 and BA0 are connected to address lines A14 and A13,
respectively."

My question is:

Is that always the case, that A14 and A13 must be connected to the BA1 and BA0 of the SDRAM chip, regardless of the numbers of used address pins?

When I issue a NOP command (LPC_EMC->DynamicControl = 0x00000183) to the EMC, the EMC registers are corrupted and the clock speed for the EMC, CPU etc is reduced?? The code keeps running but at ofcourse at extremly slow pace. Any idea why this happens? Please see attached images

I'm running the EMC clock at 120 MHz?

Thomas

[lpcware]

Content originally posted in LPCWare by Marc Crandall on Wed Jun 20 09:18:20 MST 2012
The mapping of address lines to address bits can be found here:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0269a/Bgbgcgbf.html

Note, this changes based on the type of memory you are using.

Also note that the EMC of the LPC1788 is ony rated to 80MHz not 120MHz and the EMC clock is feed from the CPU clock not the MUX as shown in the diagram above.  This means that when your CPU is running at 120MHz the max your EMC can run at is 60MHz (CPU/2)

MAC

[lpcware]

Content originally posted in LPCWare by PhilYoung on Fri Jun 01 18:02:32 MST 2012
This is a little confusing,
A13,A14 PINS are always connected to the bank select pins, but they are not always connected to CPU address bits A13,A14.

Although you have to connect it this way, the actual address bits driving these pins is determined by the collumn address length and the mode (row,bank,collumn, or bank,row,collumn ). This is important when setting the mode register in the sdram.

regards

Phil.

[lpcware]

Content originally posted in LPCWare by ole.reinhardt on Fri Jun 01 02:07:16 MST 2012
Hi Thomas,

> is that always the case, that A14 and A13 must be
> connected to the BA1 and BA0 of the SDRAM chip, regardless
> of the numbers of used address pins?

Yesterday I got an answer from the NXP guys, as I had the same question.

YES A13 and A14 (when using a 4 bank sdram) must always be connected to the sdram bank select lines, regardless of the number of address lines the sdram uses.

I hope this will help you and others a little...

Bye,

Ole Reinhardt