EMC = ARM PrimeCell MultiPort Memory Controller (PL172) TM Revision: r2p4?

[lpcware]

Content originally posted in LPCWare by starblue on Wed Feb 04 04:28:58 MST 2015
Hi,

I'm trying to better understand the timing parameters for the static memory interface of the EMC (STATICWAITx),
in order to configure it for Anybus CompactCom M30/M40 modules.

The user manual is not much help, in particular there are no timing diagrams explaining the effect of the parameters.

I found ARM document DDI 0215E "ARM PrimeCell MultiPort Memory Controller (PL172) TM Revision: r2p4",
which seems to match the EMC. (There are also somewhat different PL175 and PL176.)

Can somebody from NXP confirm that this is indeed the EMC implementation used in the LPC43xx?

[lpcware]

Content originally posted in LPCWare by starblue on Mon Feb 09 08:59:55 MST 2015
Thanks for the info. I also found some helpful timing info in the data sheet. (Somehow I'm so used to always looking into the user manual that it didn't occur to me that this is the kind of information that could be in the data sheet.)

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Quote: bavarian
There are quite some posts here on LPCWare about the behavior of the static memory interface, mainly because of the burst mode operation. Reading these post might be more useful than trying to understand the prime cell description from ARM. But I will not stop you from doing this ...  8-)

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Actually I read the thread about the impossibility to turn off read bursts:
http://www.lpcware.com/content/forum/emc-generates-double-read-cycles-static-chip-selects

But I'm not yet sure what to make of that, so I wanted to bring it up later.

On the one hand it seems there is no danger that spurious reads will confuse the Anybus modules, as reads don't seem to have side effects.

On the other hand according to the documentation Anybus CompactCom 30 doesn't support bursts (the newer CompactCom 40 should be OK). However, we have a supposedly working device for CompactCom 30, with an LPC2378 which doesn't disable EMC bursts through bit 2 of the SCS register.

Also, in a first test on the LPC43xx I didn't see a burst for a 16 bit read access (2 separate /CS low periods on the oscilloscope).

[lpcware]

Content originally posted in LPCWare by bavarian on Mon Feb 09 05:44:22 MST 2015
You can read the version number of an ARM Prime Cell at register locations 0xFE0 - 0xFEC (not part of the register description in the LPC1800/4300 users manual)
For the EMC in LPC1800/4300 this means at addresses 0x4000 5FE0  - 0x4000 5FEC.

When you look into these registers you see the values:  00000072  00000011  00000034  00000007

A description of these 4 ID registers can be found here:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0194g/index.html

This means:  it is indeed a PL172 r2p4

There are quite some posts here on LPCWare about the behavior of the static memory interface, mainly because of the burst mode operation. Reading these post might be more useful than trying to understand the prime cell description from ARM. But I will not stop you from doing this ...  8-)

Regards,
NXP Support Team.