Does the LPC2368FBD100 WDTOF bit work as written in the user manual?

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Does the LPC2368FBD100 WDTOF bit work as written in the user manual?

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Contributor I

The user manual indicates the bit is reset to 0 by a hardware reset (low pulse applied to RESET_F pin). Every board we tested, the WDTOF bit is always set to logic 1 following a normal power up. Multiple hardware resets (no power cycle) do not clear it. It's also set after a normal power up. The only way we've been able to clear it is to write 0 to that bit in the register with the software. Unfortunately that doesn't allow us to use the bit. We only want the bit to be set following a legitimate watchdog timeout event. If it is set following each power up or HW reset, it's useless to us. Is it possible for the flag to be set before the watchdog is even enabled? Just wondering if this is expected operation? Any other register settings that could affect this bit operation?

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NXP Employee
NXP Employee

Hi Allen,

On the following link you could find useful information regarding detecting the reset cause on the LPC MCUs:

https://www.lpcware.com/content/forum/lpc43xx-windowed-watchdog-timer-reset-flag

Hope this will be useful for you.
Best regards!
/Carlos
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