Correct power sequence for LPC 43xx (and probably others, too)

[michaelhermann0]

Hello,

until now we have used several LPC43xx designs with identical VDDREG (core) and VDDIO.

For the next design we plan to split the supplies. VDDREG shall be set to 2.5V, provided by a DC/DC converter, and VDDIO by another DC/DC converter.

The reason is that we want to keep the chip cooler, since at 3.3V VDDREG it can get quite hot.

Unfortunately I cannot find the information required for correct power sequencing. The data sheet recommends strongly to tie both power domains together, but this is of course exactly what we want to avoid.

My questions are:

1. Is there a correct sequence or another constraint when applying/removing power?

2. Can I use the USB0 interface with VDDIO <3.0V as long as I provide 3.3V at USB0_VDDA3V3 and USB0_VDDA3V3_DRIVER?

The data sheets shows a separate power domain for the USB interface but also notes (Note 17) that "3.0V_VDDIO < 3.6V for USB operation. Guaranteed by design".

Seems strange, and what is exactly guaranteed?

I apologize if that has been discussed before - couldn't find any matching topic with the search option.

Best regards,

Mike

(was mch0 on lcpware).

[martin_maurer]

I can't help much, but I want to point you to errata of LPC43xx, especially point OTP.1 (and page 26) of it.

[michaelhermann0]

Hi MM,

thanks for the info!

Although we don't need the OTP feature, the timing diagram you pointed out  at p. 26 did help me!

Best regards,

Mike