Circuitry om GPIO pin

[lpcware]

Content originally posted in LPCWare by IanB on Mon Apr 20 13:22:27 MST 2015
What is the INTERNAL protection circuitry on a GPIO pin? Could someone give me a circuit diagram.

[lpcware]

Content originally posted in LPCWare by embd02161991 on Wed Apr 29 09:42:34 MST 2015
Hi Ian,

The ESD box is a standard cell consisting of diodes (reverse biased) or ground gated nmos to clamp the transient.

Thanks
NXP Technical Support

[lpcware]

Content originally posted in LPCWare by IanB on Thu Apr 23 13:38:48 MST 2015
Come on LPCadmin, what's the answer?

[lpcware]

Content originally posted in LPCWare by IanB on Mon Apr 20 23:16:53 MST 2015
Yes, folks. What's in the box?

Every other manufacturer tells us!

Normally a bit of series resistance is all that's needed and the diodes to VDD and VSS take care of the rest, but if there's no VDD diode, do I need a zener to stop damage from positive-going spikes?

[lpcware]

Content originally posted in LPCWare by R2D2 on Mon Apr 20 16:23:23 MST 2015

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Quote: embd02161991
Please check the "Standard I/O pad configuration" section in the datasheet.

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:D

...which is showing a mysterouis ESD box...

[lpcware]

Content originally posted in LPCWare by embd02161991 on Mon Apr 20 16:13:30 MST 2015
Hi Ian,

Please check the "Standard I/O pad configuration" section in the datasheet.

Thanks
NXP Technical Support