Can M0+ set theMCU to go in deep sleep or power down states?

[lpcware]

Content originally posted in LPCWare by filartrix on Tue Jul 14 07:23:11 MST 2015
Hi all,
thank to you I undestrood that low power modes, different from "POWER_SLEEP" in function:

void Chip_POWER_EnterPowerMode(POWER_MODE_T mode, uint32_t peripheral_ctrl);

affect both cores (i.e. If I use Power Down for M4, also M0+ will be in power down mode)

I made some tests to manage power policy from M0+, it seems that the M4 can put the MCU only in sleep mode (WFI). If I call from M0+ the following function:

    
 /* M0+ code */
 /* Set voltage as low as possible */
        Chip_POWER_SetVoltage(POWER_LOW_POWER_MODE, Chip_Clock_GetMainClockRate());
        /* Now enter sleep / power down state */
        Chip_POWER_EnterPowerMode(POWER_DEEP_SLEEP, (SYSCON_PDRUNCFG_PD_WDT_OSC | SYSCON_PDRUNCFG_PD_SRAM0A | SYSCON_PDRUNCFG_PD_SRAM0B));

the board consume exactly the same power asif I call the function:

    
 /* M0+ code */
 /* Set voltage as low as possible */
        Chip_POWER_SetVoltage(POWER_LOW_POWER_MODE, Chip_Clock_GetMainClockRate());
        /* Now enter sleep / power down state */
        Chip_POWER_EnterPowerMode(POWER_SLEEP, (SYSCON_PDRUNCFG_PD_WDT_OSC | SYSCON_PDRUNCFG_PD_SRAM0A | SYSCON_PDRUNCFG_PD_SRAM0B));

is there anyway I could control power state from M0?
Thank you
Filippo

[lpcware]

Content originally posted in LPCWare by nerd herd on Wed Jul 15 10:48:15 MST 2015
Hi filartrix,

The heart rate sensor AN actually uses this register to allow the Cortex-M0+ core enter Power-down mode...maybe you can use that as a reference. In the meantime, I will double check what you say and submit a documentation error if needed.

https://www.lpcware.com/content/nxpfile/heart-rate-monitor-using-low-power-lpc5410x

[lpcware]

Content originally posted in LPCWare by filartrix on Wed Jul 15 06:15:52 MST 2015
Hi,
I think that there is a mistake in the user manual, Table 81.
from that table it seems that to write CPUCTRL register I  need to write the following:

0xC0C480xx

where 0xC0C4 comes from (in table 81, last line):
31:16 - - Must be written as 0xC0C4 for the write to have an effect. -

80 comes from (table 81 second-last lines):
14:7 - - Reserved. Read value is undefined, only zero should be written. -
15 - - Must be written as a 1. -

and xx are the user configuration bits.

I noticed that such command does not work, I need to write instead: 0xC0C400xx, thus I suppose there is an error in the second last line of table 81:
15 - - Must be written as a 1. -.


More in detail the value I write in CPUCTRL register is: 0xC0C4000D

Please, let me know If I'm wrong

[lpcware]

Content originally posted in LPCWare by filartrix on Tue Jul 14 09:03:13 MST 2015
Dear nerd herd
thank you very much, I did not notice the table 81.
to write bit 6 I've prepared the following code:

#define CPUCTRL_ADDR       0x40000300
#define READ_CPUCTRL()     (*(volatile uint32_t *)CPUCTRL_ADDR)
#define WRITE_CPUCTRL(val) ((*(volatile uint32_t *)CPUCTRL_ADDR) = (val))

WRITE_CPUCTRL(0xC0C4800D);
cpuctrl = READ_CPUCTRL();

I'm writing 0xC0C4800D since on table 81 last two lines are:
15 - - Must be written as a 1. -
31:16 - - Must be written as 0xC0C4 for the write to have an effect. -

but the bit 6 was 1 and remains 1, when I try to read CPUCTRL I always read 0x4D, I would like to read 0x0D.
Maybe i'm making a trivial mistake, I'll double check what I'm doing.
Thanks
Filippo

[lpcware]

Content originally posted in LPCWare by nerd herd on Tue Jul 14 07:55:33 MST 2015
Hi filartrix,

What you are experiencing is what should happen. There is a register that controls the interaction between the Cortex-M4 and Cortex-M0+ core (such a who is master and who is slave). The default setting is such that the Cortex-M4 core owns the low power modes and the Cortex-M0+ core can only put itself into Sleep mode. If you want the Cortex-M0+ core to be able to put MCU into any of the other three low power modes, you will need to clear bit 6 in the CPUCTRL register. Please take a look at Table 81 of the UM:

http://www.nxp.com/documents/user_manual/UM10850.pdf

Hope this helps!