Bus contention on LPC43xx

[danielgoertzen]

I am trying to understand if 2 (or more) bus masters can *simultaneously* move data through the bus matrix as long as they are talking to different slaves.

My scenario is GPDMA moving data from SGPIO to a RAM buffer while USB0 moves another RAM buffer onto the wire.  My concern is that bus contention might make the DMA transfer take too long and lose data.  Can I avoid bus contention by assuring that the RAM buffers are on different SRAMs?

[jeremyzhou]

Hi Daniel Goertzen,

The GPDMA has the arbitration mode, if the DMA controller is transferring data for the lower priority channel and then the higher priority channel goes active. it completes the number of transfers delegated to the master interface by the lower priority channel before switching over to transfer data for the higher priority channel. In the worst case this is as large as a one quadword.

So the lower priority channel can be suspended, however it may miss or lose continuous transferring data while the higher priority DMA channel are working.

I'd highly recommend you to do some test, then optimize the implementation.

Hope it helps.
Have a great day,
Ping

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[danielgoertzen]

Thanks for the response, but I was asking about contention between bus masters, not about contention between DMA channels.

To answer my own question, I found some useful info at https://www.doulos.com/knowhow/arm/Migrating_from_AHB_to_AXI/ .  The useful part is:

"Consequently, multiple masters can talk to multiple slaves concurrently, as long as no two masters don't try to access the same slave at the same time. Think of a DMA controller moving data from a receiver into a memory region, while the processor continues to execute code in a different memory region."