Binary point when PRIGROUP is b000

[lpcware]

Content originally posted in LPCWare by bk_huang on Tue May 10 00:14:29 MST 2016
Hi:

1. The AIRCR reset value is 0xFA050000 and PRIGROUP, bits[10:8], is b000 which value is not defeined in UM10360's table 661.
2. Or Does it mean that PRIGROUP need to be set after reset rather than use default value?

[img]Priority.png[/img]

[lpcware]

bump

[lpcware]

Content originally posted in LPCWare by bk_huang on Wed May 11 20:46:02 MST 2016
I got the point. Thanks for clarifying

[lpcware]

Content originally posted in LPCWare by starblue on Wed May 11 10:44:25 MST 2016
It's normal that NXP implements only 5 bits for interrupt priorities, anything between 3 and 8 bits is possible (see DUI552, section A-1 Cortex-M3 Implementation Options).
With only 5 bits implemented the values b000 and b001 would have the same effect as b010, so NXP didn't document them.

[lpcware]

Content originally posted in LPCWare by bk_huang on Tue May 10 18:34:04 MST 2016
Thank, I check the DUI0552 however the table 4-18 which setting is different to UM10360's table 661.
table4-18
[img]https://www.lpcware.com/system/files/table4-18_0.png[/img]
table 661
[img]https://www.lpcware.com/system/files/table661_0.png[/img]

Refer to DUI0552, PRIGROUP determines the split of group priority from subpriority. If follow table4-18, the b000 is fine for device but table 661 also mentioned that Bits [2:0] are not used in LPC176x/5x devices. I wonder that NXP change the core register design or it's just a document problem. I still confused that which Binary point or format is correct for LPC176x/5x.

[lpcware]

Content originally posted in LPCWare by starblue on Tue May 10 12:11:16 MST 2016
You can leave it at the default value of 0.
This means that any interrupt of a higher priority can preempt any interrupt of lower priority, which is what you want most of the time.

(Has anybody ever needed interrupt priority grouping?)

AIRCR is a core register, so it is documented in the ARM documents for Cortex-M3 (e.g. "Cortex-M3 Devices Generic User Guide", DUI0552), or in the excellent book "The Definitive Guide to ARM Cortex -M3 and Cortex-M4 Processors" by Joseph Yiu.