Content originally posted in LPCWare by starblue on Tue Sep 15 04:46:14 MST 2015
The second statement is the correct one to set bit 3.
Note that LPC_GPIO0->FIOSET is not a memory cell, rather reading and writing that address has special effects (see the user manual).
In particular, writing a 1 bit causes the corresponding bit on the output to be set, while the 0 bits have no effect.
The main reason for this design is that you can set bits in an atomic operation, which avoids race conditions (see below).
If LPC_GPIO0->FIOSET didn't exist, you would have to use LPC_GPIO0->FIOPIN by first reading the port, setting your bit and then writing it back.
The problem with this is mainly that it is not atomic. For example, if there is an interrupt which resets a bit between the read and the write, then this bit will be set again, and the effect of the interrupt will be lost. This kind of bug is very nasty and hard to find, as it occurs only when the timing of the interrupt is exactly between the two instructions.
Now your first example abuses LPC_GPIO0->FIOSET as if it were LPC_GPIO0->FIOPIN, and it has the same race condition.
Note to hardware designers: It would be better to make FIOSET write-only, or return all zeros.
