BL & CL parameters in SDR-SDRAM

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BL & CL parameters in SDR-SDRAM

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NXP Employee
NXP Employee
Content originally posted in LPCWare by hamedb3269 on Sat Mar 14 01:17:15 MST 2015
hi
How BL and CL parameters to be determined?
i am using "4M*16bit*4banks" sdram.
CLK frequency = 120MHz

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NXP Employee
NXP Employee
Content originally posted in LPCWare by mc on Sat Mar 14 06:51:00 MST 2015
Hi,
BL is burst length.
The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command.

In LPC Microcontroller like LPC43xx, LPC177x_8x,LPC407x_8x it can be 4 or 8.
CL is CAS latency which is explained in JEDEC as

Quote:
The number of clock cycles occurring between the registration of a read command and the active clock transition coincident with the availability of the first resultant output data.

,

see below links.
http://www.jedec.org/standards-documents/dictionary/C
http://www.jedec.org/standards-documents/dictionary/R
























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