In my case it concerns the LPC15 with custom hardware on which the ADC channels are connected to opamp outputs. Between opamp output and ADC input there is a 10 Ohm, 100 nF LPF so there is 100 nF on the ADC input pins.
All ADC input pin voltages are fixed and show no disturbance during the entire ADC sequence.
Lowering the ADC clock frequency (below 48 MHz) lowers the negative offset.
Only an ADC clock frequency below 4MHz shows acceptable results with still a slight negative offset.
Sounds like an acquisition time problem to me. Does it also go away if you use a lower value of potentiometer?
Exactly the same here, cause and solution already found?