120 MHz operation for SWO function in debugging

[lpcware]

Content originally posted in LPCWare by tvink on Thu Sep 17 12:40:59 MST 2015
Hi,

My confusion
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I am a little confused about what the SWO function is.  I know it is for trace functions and it is referred to as "optional" in the LPC1837 users manual.  But is it "necessary" for ARM debug mode without trace?
I am planning on running at 180 MHz and I see that SWO wont work if the CPU core is greater than 120 MHz.

I am planning on using an LPC Link-2 pod with LPCxpresso. 

I see mention in chapter 46 that the debugger comes up in JTAG mode and then switches to ARM Mode.  So what is the DBGEN pull up/down resistor for?

My questions
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- To use LPC Link 2 with my 180MHz CPU should I pull up or down on the DBGEN pin for best debug (without trace) experience?  I.E. quick interaction... most break points.... etc.


Thanks,
Tony

[lpcware]

Content originally posted in LPCWare by tvink on Mon Sep 21 05:48:00 MST 2015
Thanks...  will leave DBGEN high...

Tony

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Fri Sep 18 02:56:12 MST 2015
If you want to do debug - regardless of whether that is over JTAG or SWD, then you need DBGEN pulled high.

And with regards to clock frequency for doing SWO Trace - I'm not sure where the limit of 120 MHz is the user manual comes from. We have not seen any issues doing this at 180 MHz (LPC18xx) / 204 MHz(LPC43xx) in our testing of LPCXpresso's SWO trace functionality.

Regards,
LPCXpresso Support

[lpcware]

Content originally posted in LPCWare by tvink on Thu Sep 17 14:17:44 MST 2015
Thanks...

Just to be sure I understand your "opinion", DBGEN does not affect SWD just JTAG.  But sense we enter SWD from JTAG I need JTAG enabled via the pull resistor on DBGEN.

Tony

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Thu Sep 17 13:24:53 MST 2015
NB: this is opinion, not verified fact.

DBGEN pin switches JTAG between debugging and boundary scan. So is required in my opinion.

Switching to SWD from JTAG sends a specific sequence of transitions on the JTAG TMS and TDO (in to the chip) lines
so (again opinion) DBGEN needs to be set as directed and SWO (TDI) not required..

Halting debug (break points) and register/memory acces (in SWD) does not use the SWD out pin (that is for trace and instrumentation).
So (again opinion) you should be ok for 'standard' debugging.

Cheers, Mike.