How peripheral registers (PORT, GPIO, I2C, FTM) can be directly accessed (modified) using “C” or “C++” ?
For example Using K64 in KSDK 1.3 all registers are defined in “MK64F12.h”. Using KSDK 2,0 in the same named file peripheral registers definition is missing.
Thanks
Yes I already have done it myself.
Using KSDK v2.0 I have two working Edge aligned PWMs projects,
One without API only registers configuration and the other using FTM API.
BR
Shaul :smileywink::smileycheck:
My problem is with Channel(n) Status And Control (FTM0_C0SC, FTM1_C0SC … ),
How to define array of n.
I’m not familiar with those definition in MK64F12.h
struct { /* offset: 0xC, array step: 0x8 */
__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
__IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
How to define CnSC and CnV ??
Shaul
Hi, Shaul,
How about using the code:
access FTM0 register:
FTM0->CONTROLS[0].CnSC=0x0000; //access the FTM0_C0SC
FTM0->CONTROLS[1].CnSC=0x0000; //access the FTM0_C1SC
FTM0->CONTROLS[0].CnV=0x0000; //access the FTM0_C0V
FTM0->CONTROLS[1].CnV=0x0000; //access the FTM0_C1V
access FTM1 register:
FTM1->CONTROLS[0].CnSC=0x0000; //access the FTM1_C0SC
FTM1->CONTROLS[1].CnSC=0x0000; //access the FTM1_C1SC
FTM1->CONTROLS[0].CnV=0x0000; //access the FTM1_C0V
FTM1->CONTROLS[1].CnV=0x0000; //access the FTM1_C1V
Hope it can help you
BR
Xiangjun Rong
Thanks again
Yes I’m interested in KSDK 2.0
I’m considering to change to KSDK 2.0 and I want to compare and understand the meaning of direct register access without API.
My intention is to convert this simple example from KSDK1.3 to KSDK 2.0
#include "MK64F12.h"
static int i = 0;
int main(void)
{
SIM_SCGC5 |= 0x800;
PORTC_PCR4 = 0x400;
PORTC_PCR1 = 0x400;
PORTC_PCR2 = 0x400;
PORTC_PCR3 = 0x400;
SIM_SCGC6|=0x03000000;
FTM0_CONF=0xC0;
FTM0_FMS=0x00;
FTM0_MODE|=0x05;
FTM0_MOD=1000;
FTM0_C0SC=0x28;
FTM0_C1SC=0x28;
FTM0_COMBINE=0x02;
FTM0_COMBINE|=0x10;
BR
Shaul
Hi,
you can use the code to access FTM0 register based on SDK2.0 and KDS tools:
FTM0->CONF=0xxx; //FTM0_CONF=0xC0;
FTM0->FMS=0x0000; //FTM0_FMS=0x00;
for PORTC register access:
PORTC->PCR[4]=0xxx; //PORTC_PCR4 = 0x400;
For SIM module
SIM->SCGC6|=0x03000000;
Hope it can help you.
BR
Xiangjun Rong
typedef struct {
__IO uint32_t SC; /**< Status And Control, offset: 0x0 */
__IO uint32_t CNT; /**< Counter, offset: 0x4 */
__IO uint32_t MOD; /**< Modulo, offset: 0x8 */
struct { /* offset: 0xC, array step: 0x8 */
__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
__IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
} CONTROLS[8];
__IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
__IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
__IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
__IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
__IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
__IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
__IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
__IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
__IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
__IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
__IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
__IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
__IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
__IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
__IO uint32_t CONF; /**< Configuration, offset: 0x84 */
__IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
__IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
__IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
__IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
__IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
} FTM_Type;
Hi,
I just give an example for PORT B.
This is a structure defined in MK64F12.h
typedef struct {
__IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
uint8_t RESERVED_0[24];
__IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
uint8_t RESERVED_1[28];
__IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
__IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
__IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
} PORT_Type;
/** Peripheral PORTB base address */
#define PORTB_BASE (0x4004A000u)
/** Peripheral PORTB base pointer */
#define PORTB ((PORT_Type *)PORTB_BASE)
For example, this is a GPIO structure.
typedef struct {
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
} GPIO_Type;
/** Peripheral PTB base address */
#define PTB_BASE (0x400FF040u)
/** Peripheral PTB base pointer */
#define PTB ((GPIO_Type *)PTB_BASE)
#define GPIOB PTB
PORTB->PCR[0]=0x00; //code written by Rong
GPIOB->PTOR|=0x0001; //code written by Rong
Hope it can help you.
BR
Xiangjun Rong
RONG Thanks
I’m hardware oriented and KSDK 1.3 version is very clear option.
Yours GPIO and PORTB example is clear.
I have difficulty id understanding FTMx_CnV (x and n options)
I would appreciate if you will provide few FTM code samples like:
FTM0_CONF
FTM0_CONF
FTM0_C0SC
FTM0_C1SC
FTM0_C1V
FTM0_C2SC
FTM0_COMBINE
BR
Shaul
Hi,
I am sorry, I had thought you used SDK2.0, as you know that SDK2.0 is different from SDK1.3. If you use SDK1.3, the SDK1.3 defines a lot of Hal function, you'd better use the hal function directly. For FTM module, pls refer to fsl_ftm_hal.h for the FTM hal function.
Regarding your question how to access register for FTM. Pls refer to MK60D10.h, I copy it here, you can see how to access FTM register based on SDK1.3.
BR
Xiangjun Rong
/** FTM - Register Layout Typedef */
typedef struct {
__IO uint32_t SC; /**< Status And Control, offset: 0x0 */
__IO uint32_t CNT; /**< Counter, offset: 0x4 */
__IO uint32_t MOD; /**< Modulo, offset: 0x8 */
struct { /* offset: 0xC, array step: 0x8 */
__IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
__IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
} CONTROLS[8];
__IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
__IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
__IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
__IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
__IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
__IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
__IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
__IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
__IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
__IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
__IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
__IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
__IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
__IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
__IO uint32_t CONF; /**< Configuration, offset: 0x84 */
__IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
__IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
__IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
__IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
__IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
} FTM_Type, *FTM_MemMapPtr;
/* ----------------------------------------------------------------------------
-- FTM - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
* @{
*/
/* FTM - Register accessors */
#define FTM_SC_REG(base) ((base)->SC)
#define FTM_CNT_REG(base) ((base)->CNT)
#define FTM_MOD_REG(base) ((base)->MOD)
#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
#define FTM_CnSC_COUNT 8
#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
#define FTM_CnV_COUNT 8
#define FTM_CNTIN_REG(base) ((base)->CNTIN)
#define FTM_STATUS_REG(base) ((base)->STATUS)
#define FTM_MODE_REG(base) ((base)->MODE)
#define FTM_SYNC_REG(base) ((base)->SYNC)
#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
#define FTM_COMBINE_REG(base) ((base)->COMBINE)
#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
#define FTM_POL_REG(base) ((base)->POL)
#define FTM_FMS_REG(base) ((base)->FMS)
#define FTM_FILTER_REG(base) ((base)->FILTER)
#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
#define FTM_CONF_REG(base) ((base)->CONF)
#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
/** Peripheral FTM0 base address */
#define FTM0_BASE (0x40038000u)
/** Peripheral FTM0 base pointer */
#define FTM0 ((FTM_Type *)FTM0_BASE)
#define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
If you want to access the FTM0_C1V register, you can use the code
uint16_t temp;
temp=FTM0_CnV(1) ;