k82 : qspi clock in polling example

[EugeneHiihtaja]

Hi !

I can see in RM : "The controller supports singles,dual,
quad or octal data lines in single (SDR) or double (DDR) data rate configurations. SDR
mode supports upto 100 MHz and DDR mode supports up to 75MHz.

"

But in SDK example CLOCK_GetFreq(kCLOCK_McgPll0Clk) is taken as clock source for QSPI module

and it 120Mhz from this source.

Also SDR data rate configuration is in use. DDR enabling function exixts but not used in any place.

What is reason to use higher clock e.g. 120Mhz?

I think in VLPR power mode this clock should be set to 4 Mhz max from relevant source.

But what is right way to change QSPI clock ?

Disable QSPI interface and call full reinitialization by using qspi_nor_flash_init() full sequence or

if clock source is the same ( config.clockSource ) and it drop automatically when power mode changed,

for example SystemClock ( clock source = 0) drops from 120Mhz to 4Mhz, it is no need any QSPI reinitialization at all .

Please, suggest right initialisation sequence for QSPI for RUN - VLPR -> RUN transit.

Regards,

Eugene

[FelipeGarcia]

Hello Eugene,

Regarding your questions, the QSPI clock takes care of that in QSPI_Init to avoid the QSPI works under unsupported frequency.

If you like to change power mode, I highly recommend you to disable QSPI module before the transition. Once you are sure that the correct transition has been made you can enable QSPI again.

A similar procedure is done in qspi_polling() right before the QSPI writes to flash.

I hope this helps.

Best regards,

Felipe

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