I have checked the part of schematics, I think the SRAM circuit is okay. But for the LCD part, I do not know why you do not use the FB_OE and FB_R/W signals to access the LCD the same as the interface of SRAM?
For LCD interface, it seems that this is a FIFO model, it only need OE, CS, WE and data bus, there is not address signals, right? if it is the case, i think your schematics is okay, otherwise, latch is required to latch the low address.
Hope it can help you.