Hi,Duane,
I am sorry for the delay. Regarding your question, I have checked the K64P144M120SF5RM.pdf, I do not see the description that the IIC module of K64F supports FIFO, in other words,one Byte transfer for both transmitter/receiver will generate interrupt event or DMA request.
Of course, you can use interrupt mode or DMA mode to transfer the data, because the baud rate of IIC is 100KBPS, the interrupt frequency will be 12K, I think the K64F has enough resource to handle the interrupt. Each IIC module has an independent interrupt vector, you can enable the interrupt and write the IIC interrupt vector table with IIC ISR, it is okay. Pls refer to section 3.2.2.3 Interrupt channel assignments in reference manual of K64.
If you use DMA mode, the CPU is not involved in the data transfer. Pls refer to section 3.3.9.1 DMA MUX request sources, the IIC0 module request source is 18, the IIC1 and IIC2 is 19. You can set up the DMA so that each DMA triggering can read one byte from IIC data register and write to internal memory, or write the data register of IIC from memory.
Maybe you use different derivative of K64F, which has FIFO for IIC module. In the case, you can use interrupt or DMA to transfer data. In the ISR of IIC, you can read/write multiple words from/to IIC data register. If you use DMA, the DMA support to transfer multiple bytes in one DMA request.
Hope it can help you
BR
Xiangjun rong