Kinetis L series - DMA channel linking together with activated peripheral DMA request

[merlin69]

Hi!

I'm using Kinetis KL26128Z. Is it possible to use DMA channel linking together with activated peripheral DMA request?

E.g. DMA1 transfer'll start on TPM1 overflow event and also on DMA0 successful transfer (link to DMA1).

Thanks!

Jan

[merlin69]

The answer is yes.

[petermlakar]

A sample wold be nice.

I am trying to make a SPI slave with cyclic buffer by  linked DMA channel.

The second DMA hangs after first byte.

    SIM_SCGC6 |= SIM_SCGC6_DMAMUX;//Enable clock gate to the DMA Mux module.
    SIM_SCGC7 |= SIM_SCGC7_DMA;//Enable clock gate to the DMA module
    DMAMUX0_CHCFGn( DMA2) = 0;// reset DMAMUX Read
    DMA_DSR_BCRn( DMA2) = DMA_DSR_BCRn_DONE; // clear/reset DMA status Read
    DMA_DSR_BCRn( DMA3) = DMA_DSR_BCRn_DONE; // clear/reset DMA status Read
    DMAMUX0_CHCFGn( DMA2) = DMAMUX0_CHCFGn_ENBL | // Configure DMAMUX0 Read
                                   DMAMUX0_CHCFGn_SOURCE(DMA_TRIGGER_SPI1_RX);
    DMA_DSR_BCRn( DMA2) = DMA_DSR_BCRn_BCR(0xFFF); // max length of transfer Read
    DMA_SARn( DMA2) = (unsigned int)& SPIx_DL( SPI1);// set source address
    DMA_DARn( DMA2) = (unsigned int)cbuffin; // set destination address
    DMA_DCRn( DMA2) = DMA_DCRn_ERQ |//Enable peripheral request
                             DMA_DCRn_CS | //Cycle steal
                             DMA_DCRn_DINC | //Source increment
                             DMA_DCRn_SSIZE(0x01) |//Source size 8-bit
                             DMA_DCRn_DSIZE(0x01) |//Destination size 8-bit
                             DMA_DCRn_DMOD(0x6) |//Destination address modulo 512bytes
                             DMA_DCRn_LINKCC(0x3) |//link to LCH1 after the BCR decrements to zero
                             DMA_DCRn_LCH1( DMA3) /*|//Link DMA Channel
                             DMA_DCRn_D_REQ*/; //ERQ bit is cleared when the BCR is exhausted
    DMA_DSR_BCRn( DMA3) = DMA_DSR_BCRn_BCR(0xFFF); // max length of transfer Read
    DMA_SARn( DMA3) = (unsigned int)& SPIx_DL( SPI1);// set source address
    DMA_DARn( DMA3) = (unsigned int)cbuffin; // set destination address
    DMA_DCRn( DMA3) = DMA_DCRn_CS | //Cycle steal
                             DMA_DCRn_DINC | //Source increment
                             DMA_DCRn_SSIZE(0x01) |//Source size 8-bit
                             DMA_DCRn_DSIZE(0x01) |//Destination size 8-bit
                             DMA_DCRn_DMOD(0x6) ;//Destination address modulo 512bytes
    SPIx_C2( SPI1) |= SPIx_C2_RXDMAE; //SPI Transmitter DMA enable Write/Read

[mjbcswitzerland]

Peter

I would like to ask whether you found a solution to your problem?

If I understand it correctly you used one DMA channel to transmit/receive a certain number of bytes and, when its byte count reaches zero, you wanted to start a similar process on a different DMA channel.

I am also looking to do something similar with high speed data where an interrupt after the first buffer is complete is not adequately fast to prepare and start the second task. This means that I also took a look at the linking possibility but my understanding is that it doesn't pass the control to the second DMA channel (which would be the perfect situation and what you look to have needed) but instead the link is more a trigger for the linked DMA channel. This would possiby match with your observations since it would cause a single transfer to take place (noting that there is no trigger otherwise set up in the DMA MUX for your linked channel that would cause a peripheral to trigger it afterwards).

Did you conclude that it wasn't possible or did you find a method for the intended operation?

Regards

Mark