default pin status after reset

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default pin status after reset

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davidsunsun
Contributor I

Dear Support, 

I am a little confused about the status during the chip is holding in reset mode. 

in K24P144M120SF5, Rev 5, 12/2014

chapter 5.1 there is a column called Default, is this the pin definition when chip is hold in reset mode. 

what is the difference between Default and ALT0. noticed that all DISABLED pins in Default column, there are empty in ALT0 column. 

is the DISABLED means the pin is put in Hi-Impedance( disconnected). 

in K24 Sub-Family Reference Manual(K24p144M120SF5RM.

in table 10-2, Pin mux at reset. most of the port are ALT0.  

Here is why I ask this question.  in our design, we connected Pin C4 and D5 to a uart port. I want to know what is the status ( voltage level if we have 1M ohm pull down resistor) during reset. 

second question is if the chip is brand new, not programmed. what is the pin C4 and D5 status after reset?

third question, if I use freescale KDS 3.2.0. "flash from file function", in Debugger function. I checked "Mass erase on connect" without any "preserve" and didn't assign a symbols or a file in Startup Menu. if I execute Flash. I believe the tools will do a "mass erase on connect" and failed to flash a new image to the chip. 

is the chip in default factory status after this mass erase? what is the expectation of the pins out of reset?  if the chip is in a unknown status, is there a simple way to reset the chip to factory default use Freescale KDS or any other tools?

thanks,

David Sun

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, David

Regarding the pin status during and after Reset, pls refer to section 10.3.1 K24 Signal Multiplexing and Pin Assignments in RM of K24. In detail, all analog pins remain the ananlog function. For digital pins, the  JTAG pins remain the JTAG function, for the other digital pins, they are disabled, in other words in high impedance. If you have doubts, pls list the pins you have doubts.

After mass erase, all the flash are empty(0xFF) and all flash are in unsecurity state, which is equivalent to a factory default chip.

Hope it can help you

BR

Xiangjun Rong

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davidsunsun
Contributor I

Hi XiangJun Rong,

The last question is not clear to me. if I did a mass erase to the chip. is it equivalent to a factory default chip? what is the pin status during and after the reset?

thanks,

David Sun

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, David

Regarding the pin status during and after Reset, pls refer to section 10.3.1 K24 Signal Multiplexing and Pin Assignments in RM of K24. In detail, all analog pins remain the ananlog function. For digital pins, the  JTAG pins remain the JTAG function, for the other digital pins, they are disabled, in other words in high impedance. If you have doubts, pls list the pins you have doubts.

After mass erase, all the flash are empty(0xFF) and all flash are in unsecurity state, which is equivalent to a factory default chip.

Hope it can help you

BR

Xiangjun Rong

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davidsunsun
Contributor I

thank you very much.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, David,

I think the default state is the state that the chip is during Reset and after Reset until code is executed to configure the pin to a function. The "disabled" is in high impedance.

Regarding the image you attached, if you check the "mass erase" box, the tools will mass erase the flash when you download code. Once you erase the flash, you can not recover it.

Hope it can help you

BR

XiangJun Rong

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