When is EZPort mode selected during reset on K20?

[grahamjordan]

I using K20 (MK20FX512VLQ12 specifically). It is in a system with other processors, with a 'Master' processor that can put the K20 in EZPort mode to reprogram it.

What I can't see from the documentation is exactly when the \EZP_CS line is checked to determine if is going into EZPort mode.

If the external reset pin is driven low, and then goes high. When is the \EZP_CS checked?

I see from the reference manual (K20P144M120SF3RM Rev. 3, November 2014):

"The device's functional mode is controlled by the state of the EzPort chip select

(EZP_CS) pin during reset."

In the boot sequence (step 4) it says:

"EzPort mode is selected instead of the normal CPU execution if EZP_CS is low when the internal reset is deasserted."

But this sequence seems to refer to power-up explicitly. As it also indicates it looks at the \RESET pin after this (in step 5).

When is 'internal reset' deasserted, relative to power-up, and relative to having \RESET pin driven low and then high externally?

Thanks.

[Jorge_Gonzalez]

Hello Graham Jordan:

Actually the boot sequence you find in the manual is valid for all reset modes, except for not waiting for the voltage if reset is not POR (Power On Reset).

The RESET pin is bidirectional and it is driven low internally during any reset for at least 128 bus clock cycles:

The "internal reset" mentioned in step 4 of the boot sequence is the internal Chip Reset but it is highly tied to the RESET pin, so according to the second paragraph in text above there might be 2 scenarios:

1) The MCU resets by an internal source (e.g Watchdog) -> In this case the pin is driven low internally by the MCU for ~128 bus clock cycles and the EZP_CS pin is checked as soon as the pin is released and pulled high by the pull-up resistor. You can inspect the pulse duration with a scope.

2) The MCU is reset by pulling low the RESET pin externally -> In this case the pin is also pulled low internally as in case (1) but it goes unnoticed since typically the external signal holds the pin low much longer. The EZP_CS is checked as soon as the external signal releases the RESET pin (pulled high).

I hope this helps to clarify. Let me know if you have questions.

Best Regards!

Jorge Gonzalez

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------