When does ADC sample time actually start?

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When does ADC sample time actually start?

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Contributor II

Hi all,

I'm hoping someone can provide definitive clarity about how the ADCx peripherals work on K SF3 devices, specifically as it relates to computing sample time.

I've implemented a working variant of AN5940 to implement multi-channel streaming ADC capture on several different Kinetis K SF3 devices (K60FX512VLQ12 is one).  It works like PDB -> ADC -> DMA

Per the Reference Manual, I believe in this configuration, conversion starts in the ADC at the rising edge of the hardware trigger generated by the PDB.  And, this 'conversion' includes both sample time and conversion time, in the strict sense of the two terms.

For a SAR converter, sample time actually starts when the input signal is gated to the converter.  Of course sample time is provided to allow the input capacitance of the converter to stabilize within 1/2 LSB of the input signal before actual SAR conversion beings.

What is not clear to me is when the input signal is actually gated into the ADC.  Is it:

1. When the DMA writes the new channel to ADC0_SC1A, or

2. when the ADC receives the hardware trigger from the PDB?

Thanks in advance, and sorry for the long message.

Steve

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NXP Employee
NXP Employee

Hi Steve,

In your case, the conversion starts after the ADC receives the hardware trigger from the PDB (assuming that the hardware trigger is enabled ADTRG = 1).

If the software trigger is selected (ADTRG = 0), the conversions will start after the DMA writes the ADC0_SC1A register. In any case, the conversion ends when the COCO flag is set.

You can find more detailed information in the ADC chapter for your microcontroller under the section Conversion Control --> Initiating conversions.

I hope this information helps :smileyhappy:

Saludos

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Contributor II

Hi Santiago,

Yes, I understand the reference manual (RM) states conversion starts upon receipt of the hardware trigger.  I mentioned this in my question. :smileywink:

I think I can answer my own question.  Since the PDB is capable of triggering either ADCx_SC1A or ADCx_SC1B, the earliest that the peripheral could gate the input to the sample cap, at least in a consistent manner, would appear to be at the onset of the hardware trigger.

If this logic holds true in silicon, then where the RM uses the term "conversion", it is often referring to the entire SAR capture process, which includes both sampling and conversion.

Is there a timing diagram of the ADC peripheral available anywhere?  That would go a long way to clarifying timing related behaviors.

Thanks,

Steve

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Senior Contributor I

In this case I suggest you to consider the time description for the formula (Figure 39-157. Conversion time equation)

conversionTime.JPG.jpg

You will need to check also:

  • Table 39-177. Single or first continuous time adder (SFCAdder)
  • Table 39-178. Average number factor (AverageNum)
  • Table 39-179. Base Conversion Time (BCT)
  • Table 39-180. Long sample time adder (LSTAdder)
  • Table 39-181. High Speed Conversion time Adder (HSCAdder)

On the table for Long sample time adder you notice you can chose different times for conversion based on ADCCK (ADC clock) units, from this information you can determine ADC interactions along sampling and conversion time.


Have a nic day :P,
Perla

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