What and How the SS functionality?

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What and How the SS functionality?

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pietrodicastri
Senior Contributor II

Good morning

I need to find the documentation for using the SS pin in slave mode.

The RM is here and there referring to the SS signal, but

1) I don t see where this pin is, maybe is overlapped with one PCS ????

2) Is it mandatory to use it? Is somewhere written how to select/deselect the usage?

3) If I choice not to use, how to handle the transfer initiated and aborted by a master? (the fraction of data..)

Thank You

Pietro

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Pietro,

The SS is overlapped with the SPIx_PCS0, it's illustrated in the Chapter 10: Signal Multiplexing and Signal Descriptions in the RM and you can find it, the Fig1 shows K60 SS pin allocation.

If you set the SPI interface work in Master mode, the SS pin will be invalid automatically, however when the SPI work in Slave mode, the SS pin will be valid.

Once the Slave mode in MCR[MSTR] is configured, the module is enabled by clearing MCR[HALT] and it should be ensured that module Slave is enabled before enabling it's Master.

After the previous configurations, the Slave modes will initializes successful.
Have a great day,
Ping

2015-02-28_10-50-17.jpg

                                                                        Fig 1

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Pietro,

The SS is overlapped with the SPIx_PCS0, it's illustrated in the Chapter 10: Signal Multiplexing and Signal Descriptions in the RM and you can find it, the Fig1 shows K60 SS pin allocation.

If you set the SPI interface work in Master mode, the SS pin will be invalid automatically, however when the SPI work in Slave mode, the SS pin will be valid.

Once the Slave mode in MCR[MSTR] is configured, the module is enabled by clearing MCR[HALT] and it should be ensured that module Slave is enabled before enabling it's Master.

After the previous configurations, the Slave modes will initializes successful.
Have a great day,
Ping

2015-02-28_10-50-17.jpg

                                                                        Fig 1

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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pietrodicastri
Senior Contributor II

Thank You..

Now this aspect is clear.

I would need an additional answer if it is possible for You. Please.

Is this SS signal mandatory? In your answer I read the pin is valid.

So no way to work without the SS??

Another mumble I have is in the naming. I need to know if the SOUT pin is the output

for both master and slave. Same of course for the SIN. From the document it appears yes,

Thank You

Pietro

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Pietro,

If you decide to work in slave mode, the SS pin is only way to active the peripheral chip selection, however this pin need to be asserted manually.

No matter which mode been selected, The SOUT pin will keep output permanently, of course the SIN is same too.

Wish it helps.
Have a great day,
Ping

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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pietrodicastri
Senior Contributor II

Ok

Thank You

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