Watchdog Reset Count register

[angae]

Hi everyone,

I'm working on a MK70FN1M0VMJ15.

I correctly use the watchdog registers in order to monitor, reset and keep track of watchdog reset Issue.

I'm using the WDOG_RSTCNT register (4005_2014h) in order to check how many times my target resets due to watchdog.

I saw that this counter reset when a POR (Power On Reset) occurs (I turn-off and then turn-on my board), but I need a way to reset this register also in some particular circumstance.

I read from Datasheet (page 641):

Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing 1 to the bit to be cleared enables you to clear the contents of this register.

I didn't understand the last sentence. What's the meaning of "writing 1 to the bit to be cleared" ?

My question is:

Can I reset this register? If yes, how?

Best regards,

Francesco

[angae]

I was able to find a solution by myself. I write it here because maybe it could usefull to someone else.

The answer is YES, it is possible. The following stpes show how to do:

[pseudo-algorithm]

0. Start to Unlock the registers (put WDOG_STCTRLH[4] =1, this is the ALLOWUPDATE field).

1. Init the unlock procedure (write the sequence 0xC520 - 0xD928 within the correct time window).

2. Wait 1 BUS CLK Cycle

3. Write 0xFFFF to WDOG_RSTCNT (fill it with '1', this will restart the counter)

4. Wait 20 BUS CLK Cycles.

5. Repeat step sfrom 0 to 2 and then go to 6.

6. Lock the registers (put WDOG_STCTRLH[4] =0, this is the ALLOWUPDATE field).

7. Wait 20 BUS CLK Cycles.

Maybe this is not the most clean way, but it works for me.

Best regards,

Francesco