Hi
The Cortex has a flexible interrupt controler whos interrupt vector table can be pointed to almost any location (Flash/RAM).
This means that you can have multiple interrupt vector tables or you can enter functions in a single one in SRAM.
The advantage of the SRAM based one is that it is easy to change individual interrupt handlers at run time without having to change the whole table. If minumum SRAM use is a requirement relocating fixed Flash tables may be preferred, but the SRAM based method is certainly simpler to maintain.
Regards
Mark
P.S As comparison with Coldfire - the interrupt vector can be located only to 2Meg boundaries (if I remember correctly). Since the internal SRAM and internal Flash is generally much smaller than this there are only two choices - start of FLASH or start of SRAM. In the case fo Coldfire boot loaders it means that you have to use an SRAM based table or else invent a jump table method from fixed vectors in the boot loader - SRAM being of course much easier to maintain again.