Using external DDR2 on TWR-K70F120M

[laluquethibaut]

Hello,

I start to work on the kinetis TWR-K70F120M demo board to prototype a client application requiring an extended RAM size. I chose this board because an external 1GB DDR2 RAM is integrated.

I 'd like to use this external RAM without an operating system (MQx or other). I'm using Code Warrior.

I'm trying to configure manually the DDR controller with the processor expert. Please, can you explain me step by step how to configure the project to work with the external DDR2 and how can I use it ?

Thanks

[apanecatl]

Although we don’t have any fully implemented DDR use example code, you can use the configuration file included in the KINETIS_120MHZ_SC.zip example folder, this is the folder path:

KINETIS_120MHZ_SC\build\iar\ config files\

The folder can be downloaded from the following link:

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=K70_120&nodeId=01624698C9DE2DDDB1&fps...

Under Software development > Snippets, Boot Code ….

[laluquethibaut]

Dear Pedro, Thanks for the answer,

I'm trying to use the example lcdc included in KINETIS_120MHZ_SC\src\projects. This example uses the external DDR on the K70F120M demo board.

After including all needed files, the project compiles and can be loaded on the target. However, during the program execution, the processor crashes (and the debugger too) on the first DDR controller register in the function twr_ddr2_script_init().

I'm trying to start a new Code Warrior project to integrate only this function. As above, the processor crashes on the first instruction involving a DDR register (DDR_CR00)., The clock device is configured with the processor expert to use the external 50MHz clock and the PLL0 as a source for the master clock. The coreclock is at 120MHz, the bus clock at 60MHz as the external bus clock and the flash clock is at 20MHz.

Here the code of this function :

void twr_ddr2_script_init(void)

{

   /* Enable DDR controller clock */

  SIM_SCGC3 |= SIM_SCGC3_DDR_MASK;

  /* Enable DDR pads and set slew rate */

  SIM_MCR |= 0xC4;   // bits were left out of the manual so there isn't a macro right now

  DDR_RCR |= DDR_RCR_RST_MASK;

  * (volatile unsigned long *)(0x400Ae1ac) = 0x01030203;

  DDR_CR00 = 0x00000400;    // DDRCLS = 4 is reserved??

  DDR_CR02 = 0x02000031; 

  DDR_CR03 = 0x02020506;

  DDR_CR04 = 0x06090202;

  DDR_CR05 = 0x02020302;

  DDR_CR06 = 0x02904002;

  DDR_CR07 = 0x01000303;

  DDR_CR08 = 0x05030201;

  DDR_CR09 = 0x020000c8;

  DDR_CR10 = 0x03003207;

  DDR_CR11 = 0x01000000;

  DDR_CR12 = 0x04920031;

  DDR_CR13 = 0x00000005;

  DDR_CR14 = 0x00C80002;

  DDR_CR15 = 0x00000032; //  | DDR_CR15_SREF_MASK ;

  DDR_CR16 = 0x00000001;

  DDR_CR20 = 0x00030300;

  DDR_CR21 = 0x00040232;

  DDR_CR22 = 0x00000000;

  DDR_CR23 = 0x00040302;

  DDR_CR25 = 0x0A010201;

  DDR_CR26 = 0x0101FFFF;

  DDR_CR27 = 0x01010101;

  DDR_CR28 = 0x00000003;

  DDR_CR29 = 0x00000000;

  DDR_CR30 = 0x00000001;

  DDR_CR34 = 0x02020101;

  DDR_CR36 = 0x01010201;

  DDR_CR37 = 0x00000200;

  DDR_CR38 = 0x00200000;

  DDR_CR39 = 0x01010020;

  DDR_CR40 = 0x00002000;

  DDR_CR41 = 0x01010020;

  DDR_CR42 = 0x00002000;

  DDR_CR43 = 0x01010020;

  DDR_CR44 = 0x00000000;

  DDR_CR45 = 0x03030303;

  DDR_CR46 = 0x02006401;

  DDR_CR47 = 0x01020202;

  DDR_CR48 = 0x01010064;

  DDR_CR49 = 0x00020101;

  DDR_CR50 = 0x00000064;

  DDR_CR52 = 0x02000602;

  DDR_CR53 = 0x03c80000;

  DDR_CR54 = 0x03c803c8;

  DDR_CR55 = 0x03c803c8;

  DDR_CR56 = 0x020303c8;

  DDR_CR57 = 0x01010002;

  asm("NOP");

  DDR_CR00 |= 0x00000001;

  while ((DDR_CR30 & 0x400) != 0x400);

  MCM_CR |= MCM_CR_DDRSIZE(1);   

}

Someone can help me to find the problem ?

[laluquethibaut · Accepted solution]

Hello,

We have solved our memory problem. The twr_ddr2_script_init() function is working correctly, but before calling it some initialization must be done.

The DDR controller need the clock provided by the PLL1 output to work properly. If the PLL1 is not enabled and not set correctly, the CPU crashes (if the interrupt is not trigged) when you try to access to one of the DDR register.

For the TWR-K70F120M demo board, you can configure correctly the DDR controller with these steps (perform it with the processor expert) :

- Enable the oscillator 0 and select its source as the external reference clock 50MHz source.

- In the clock source setting, select the PEE mode for the MCG mode. Select the external reference clock source for the MCG as the system oscillator 0 and select the PLL1 module.

- Under the PLL1 settings, enable the PLL and for a maximum performance, configure the PLL output for a 120MHz.

- Finaly, Under the clock configuration 0, define the Core clock at 120MHz, the internal and external bus clock at 60MHz and the flash clock at 20MHz.

In your C code, after the PE_low_level_init() call, put your twr_ddr2_script_init() function. The external DDR is now initialized.

You can access it with a pointer. The DDR memory space start at 0x80000000 and have a size of 134184960 Bytes.

We have perform some speed tests and the best result are obtained with the 64 bits word transfert with a speed transfert of 208Mbits/s (that it's better than the 32,16 or 8bits transfert).

[ejwords]

I just wanted to say a quick "Thank you" for posting the information here on getting the DDR2 controller going.

I followed the instructions in your post & had it up & running in 5 mins - this saved me a heap of time!

All the best,

Ewan J. Wordsworth

Microbee Technology Pty Ltd.

www.microbeetechnology.com.au

[terrybiberdorf]

I followed your suggestions with success and I have code that will perform memory tests with success.

My problem is that Code Warrior will not display the memory to view or modify directly? When I perform a memory view all I receive is ???????, which I originally was as indication that the DDR was not initialized.

Thanks

[brianpaterson]

Interesting!

I wonder if there is any reason that this cannot be implemented on the K60 series.

Any thoughts from Freescale?

I suspect that I'd need to use notebook memory rather than desktop due to space limitations.

It will lie almost flat against the main board.

Cheers,

Brian

[apanecatl]

Nice to hear you were able to solve the issue, I have absent from the communities for some time and I just reviewed your post, keep us posted if you need anything else!!