Updating FTM_CnV pulls down GPIO

[snipex94]

Hi!

As I mentioned in the title, I have a bug in my code. Every time that I want to update FTM_CnV register (doesn't matter if 0 or 1 or any number) PTA2 GPIO goes low. I can't find any reason for this.

Do you have any ideas for what may be causing this?

[egoodii]

What 'ALT pin function selection' do you have placed for PTA2?  It defaults to JTAG/SWO output.  I assume this is NOT a 'debug connected' environment...

[snipex94]

This is a debug connected environment but the SWD pins are at PTC4 and PTA4 (I don't have a JTAG interface). I forgot to mention that I use S9KEAZN64 mcu. Peripherals connected to PTA2 are KB interrupt, UART0 and I2C0, but I am not using them. I'm only using UART1 if this means anything. 

Below is a picture from the reference manual for PTA2 pin.

Update: Since that this issue is not caused by updating FTM_CnV register (it was just my luck that it pulled down the pin at the same time multiple times in a row).

I set a breakpoint at the beginning of the while loop and counted how many times it looped before pulling down the pin.

It was always the same number of times.

This problem is just weird and I would love some help on this.

[xiangjun_rong]

Hi, Kvas,

As you know that the PTA2 is open drain pin, if you use it in GPIO output mode, an external 5K~10K ohm pull-up resistor is required. Even if you set the PTA2 in input mode, I also suggest you connect an external 5K~10K ohm pull-up resistor.

anyway, pls connect a pull-up resistor and have a try, I suppose what you see is noise if you do not connect pull-up resistor.

BR

Xiangjun rong