Two pwm out of phase

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Two pwm out of phase

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EmanueleP
Contributor II

Hi, i have a kea 128 and i want to generate 2 out of phase PWM signals. I have selected FTM2 ch0 and ch1 for my purpose. PWM signals duty cycle must be 60%. Could you help me please?

 

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EmanueleP
Contributor II

I solved the problem by setting a channel with ELSnA = 1. So the output channel become 1 at the match up, to the counter overflow

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_Leo_
NXP TechSupport
NXP TechSupport

Thank you so much for your interest in our products and for using our community.

In S32 Design Studio for ARM there is an example for PWM (FTM_PWT_kea128), which can serve as a reference.

Hope it helps you. Please let me know if you have more questions about it.

Have a nice day!

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EmanueleP
Contributor II

 Thanks for your help, but i'm trying to configure the two PWM signals as shown in the picture. 

I don't know if this type of configuration is supported by a single FTM module or if i'm forced to use 2 FTM modules: one channel of FTM0 in edge-aligned mode and one channel of FTM1  in center-aligned mode.

Thanks.

Shift phase.jpg

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_Leo_
NXP TechSupport
NXP TechSupport

It is possible to configure the channels of the same FTM module differently. So yes, you only need one module.

However, for what you are looking for, it may be more convenient to make a Phase-shift PWM signal, for more details about this please refer to section 3.4 of application note AN5142.

Hope it helps you.

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EmanueleP
Contributor II

So, in this way i have to use 4 channels? In this way i lose 2 channel.

Thank you for your support.

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_Leo_
NXP TechSupport
NXP TechSupport

Sorry, could you clarify your question please?

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EmanueleP
Contributor II

I would like to use two FTM channels to have 2 output singals with different phase. To use the application note method I need 4 FTM channels if I'm not mistaken. Now i'm try tu use ELSnA on one channel to set Low-true pulses (set Output on match-up) (26.3.6 chapter of kea128rm manual).

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2,855 Views
EmanueleP
Contributor II

I solved the problem by setting a channel with ELSnA = 1. So the output channel become 1 at the match up, to the counter overflow

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