Trouble with ADC

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Trouble with ADC

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NateBragg
Contributor I

Hello all,

 

I am new to both ARM cores and Freescale uCs, though I have done embedded development on other chips in the past. I recently purchased the TWR-K53N512 in order to evaluate the K53 chip for a custom board. As you may know, the DVD shipped with the Tower kit contains evaluation versions of both IAR Embedded Workbench V6.0 and Keil uVision V4.20.03.0, both of which are new to me, and are the focus of my evaluation.

 

One of the (many) reasons this chip appealed to me was the powerful DSP potential. As a first step, I located the Kinetis demo code package, and took a look at the adc_demo project in IAR. It worked just fine, and enabling the Serial port on the TWR-SER board enabled me view the output in hyperterminal. In order to increase my knowledge and understanding of the ADC, I attempted to create a Keil project from scratch that did a little similar behavior.

 

Unfortunately, I was not successful. Any attempt to read or write to - either ADC0 or ADC1 - CFG1, CFG2, CV1 or CV2 registers (perhaps others? I haven't tried) results in a hard fault, and I wind up straight in the HardFault_Handler provided inside the startup_MK53N512ZCMD100.s file created with the project. I'm at a loss, and I can't seem to find my way out of this. I tried as much as possible to just "straight copy" the code (with only a few tweaks needed to port) from the IAR project, so I'm not sure where I could have gone wrong.

 

Also, is there an easier way to handle the ADC than the way presented in adc_demo? This just appears to be a ridiculous amount of boilerplate in order to perform a simple function - at least 5 times as much code as I've used on other architectures. That's not really a bad thing, as I'll only really write this code once, but it leaves me with an uneasy feeling that there is a simpler setup to be found.

 

Thank you in advance!

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LuisCasado
NXP Employee
NXP Employee

Hello,

 

Regarding hardfault, it looks like you are not enabling clock for ADC0/1.

 

/* Turn on the ADC0 module clock  */
  /* Turn off the ADC1 module clock  */
  SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK ;
  SIM_SCGC3 &= ~SIM_SCGC3_ADC1_MASK ;

 

Best Regards,

 

Luis

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LuisCasado
NXP Employee
NXP Employee

Hello,

 

Regarding hardfault, it looks like you are not enabling clock for ADC0/1.

 

/* Turn on the ADC0 module clock  */
  /* Turn off the ADC1 module clock  */
  SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK ;
  SIM_SCGC3 &= ~SIM_SCGC3_ADC1_MASK ;

 

Best Regards,

 

Luis

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NateBragg
Contributor I

Thank you so much.  I was staring at this for hours.  I must have typoed when I was porting the few lines I had to port between them - somehow SCGC3 became SCGC5 which, now reading the doc, no wonder it wasn't working.

 

So, wrt my addendum question, is there a simpler way to use an ADC than with the PDB and an ISR?  On simpler chips in the past, I've just triggered and done a busy wait on a conversion complete flag, but I couldn't find any such example code for this chip.  From reading the doc it seems like this mode is possible; do you or anyone else know how to enable it?

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mjbcswitzerland
Specialist V

Hi

 

If the ADC interrupt is not enabled and the conversion complete flag is polled until it becomes set you will have the simple case.

 

Regards

 

Mark

 

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