David,
thanks for the response. the GPIO example is quite small and I got it to
go with some messing around. maybe you could verify my settings as I had
to manipulate the values used for MCG_C5 and MCG_C6 in order to get pll
lock and for the baud rate to be correct at 115200.
the original generated source in pll_init had
#if (defined(K60_CLK))
MCG_C5 = MCG_C5_PRDIV(0x18);
which expands to MCG_C5 = 0x18; I thought this strange since the manual
(K60P144M150SF3RM.pdf) shows bits 4 & 5 as read only. so this was really
MCG_C5 = 0; I changed to MCG_C5 = 5; and now the PLL is happy. the
effective baud rate was not good (through the USB cable) and so I looked
further and found
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)
again, this expands to MCG_C6 = 0x40 | 24; this value seemed much to
large. so after some experimentation and my oscope, I set it to
MCG_C6 = MCG_C6_PLLS_MASK | 7;
now the PLL is happy and the effective baud rate is 115200 as it should be.
so, did I choose correctly? is it possible in the latest release that the
macros for MCG_C5_PRDIV and MCG_C6_VDIV have changed?
On Fri, Aug 1, 2014 at 6:50 AM, David E Seymour <