S32K148 FlexCAN Only Output SOF Pulse then Enter BusOff

[April]

I developed the program in S32DS. When trying to transmit CAN frames, only a short low-level pulse  is output on the TX pin, and the subsequent ID and data bits are truncated, so complete frames cannot be sent. No data is received by the USB-CAN analyzer, and the FlexCAN controller directly enters the bus-off state.

I have checked clock configuration and register values, and tested different CAN channels, but the problem remains unsolved. I want to figure out which configuration parameter is set incorrectly. Thanks for your help.

[Julián_AragónM]

Hello @April,

From your project, configuration and routine seem to be correct. Could you please share if you are using an S32K148EVB from NXP, or if this is a custom design?

Have you tried testing the Can_example_S32K148 project included within the RTD? You can simply add the CAN0 pins and disable loop back mode to enable Tx/Rx and test the routine. 

Lastly, have you confirmed that both nodes (S32K148 and CAN analyzer) are set to the same bit timing and protocol configuration (CAN vs CAN FD)? You can use the following tool to calculate the values: MPC5xxx/S32Kxx/LPCxxxx: CAN / CAN FD bit timing calculation.

If you are using a custom design, you can refer to the S32K148 EVB's schematic and Hardware Design Guidelines for S32K1xx for the CAN interface design and recommendations.

Best regards,
Julián

[April]

Hi Julián,

Thank you for your reply. I'd like to correct and add some important details to my earlier message, which was written in a hurry.

Board: This is a third-party board (not an NXP EVB), model S32K148_REV2_Q144. Worth noting: I found errors in the seller's schematic (labeled transceiver position didn't match the actual PCB silkscreen), so the reference design documentation for this board may not be fully reliable.

Official CAN example: I did try building Can_example_S32K148, but hit environment issues unrelated to CAN itself (missing toolchain/include paths, and finally a version mismatch error between Port_Ci_Port_Ip.h and Port_Ci_Port_Ip_Cfg.h — "different vendor ids"/"AutoSar Version Numbers are different"). This looks like an RTD package version mismatch with my own project, not an IDE version issue. I'll try to resolve it, but I don't think it's central to the hardware problem.

New evidence (from my own project you already reviewed): I've done deeper verification with a logic analyzer since my last message:

1. MB8 content is 100% correct — read directly from registers right after CDD_CanTransmit(): CS=0x0C080000 (CODE=0xC pending, DLC=8), ID=0x00400304 (>>18 = 0x10, matches config), DATA=0x01020304/0x05060708 (matches my 8-byte payload exactly).

2. TX signal at the pin is correct too — probing PTE5 and the transceiver's TXD input simultaneously (200MHz logic analyzer), the two waveforms are identical, confirming the PCB trace is fine.

3. But transmission aborts after only ~8-9 bit transitions (roughly SOF + a few arbitration bits), and the controller enters Bus-Off shortly after (ESR1 confirms FLTCONF=11, TXERRCNT increments each attempt).

4. CANH/CANL show zero activity, even with the USB-CAN analyzer properly connected and 120Ω termination enabled (bus not floating). As a control test, I ran the same setup (floating vs. terminated) on a different, known-working STM32 board — CANH showed proper transitions once terminated. On my S32K148 board under identical terminated conditions, CANH/CANL remain completely flat.

5. Same result on CAN1 (different pins/transceiver).

Since MCU-side TXD is confirmed correct up to the transceiver input, but CANH/CANL never respond even with proper termination, I suspect the transceiver output stage (or something shared between both channels, e.g. supply transient behavior — I haven't been able to check this with a scope, only a logic analyzer).

Questions:

1. Does "TXD correct at transceiver input, but CANH/CANL completely flat under proper termination" more strongly suggest a transceiver hardware fault, or are there other common board-level issues (enable/standby circuit, supply decoupling) that could cause this exact symptom?

2. Is it expected for FlexCAN to abort after only the first few arbitration bits (rather than completing the full frame and failing at the ACK slot) when there's no real bus activity? Want to confirm my understanding of the bit-monitoring mechanism.

3. For the RTD version mismatch in the example project — is there a way to check which RTD version matches a given S32 Configuration Tool release, so I can get a matching example package?

Thanks again for your help.

Best regards, April

[April]

Hi Julián,

I’m really surprised and thankful for your reply to my question.I am using a self-designed hardware board; only the power supply circuit differs from the official EVB schematic, while the rest of the circuits are consistent with the reference design.

I have tested the official CAN example project. I only configured CAN0 pins without enabling and configuring the PORT module inside the MCAL layer, and the project keeps failing to compile repeatedly.

The specific compile error is: " f../board/Port_Ci_Port_Ip_Cfg.h:47:10: fatal error: Port_Ci_Port_Ip_Types.h: No such file or directory".

I have this header file available in my self-configured project files, yet after importing this official example project, this header file is not generated automatically during code generation.

Could this missing header file error be caused by mismatched IDE software versions? At present I’m developing on S32DS for S32 Platform, and I am downloading S32DS for ARM 2.2.2 to switch the development environment.

Looking forward to your guidance.Best regards,April