Using the slow 32.7KHz Internal RC for clocking, and using FLL to boost core clock up to 47.98. In the specification, it states the max core clock is 48MHz, but when using IRC and FLL, there is up to 3% error in the clocking, resulting in a core clock of ~49MHz, which exceeds the max of 48MHz.
What are the adverse effects at running the KL16 @ 49MHz?
Thanks, in advance
Scott