Question on SRAM size / availability

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Question on SRAM size / availability

Contributor I


I am using K65 MCU for my application. This has 256 KBytes of RAM (    SRAM_UPPER : 192 KB and SRAM_LOWER : 64 KB) and the access rule is as defined below.

4.12 SRAM accesses
The SRAM is split into two logical arrays that are 32-bits wide.
• SRAM_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor
• SRAM_U — Accessible by the system bus of the Cortex-M4 core and by the

backdoor port.

My question is, can my application use both these portions of the SRAM seamlessly? In other words, both the sections are available for application to use (total 256 KB) ? Are there any constraints for the use?

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Specialist V

Hi Praveen

Generally the SRAM can be considered as a linear 256k block of memory as long as a couple of things are considered:
1. Mis-aligned accesses across the boundary are not supported; this is generally not an issue since one should "generally" avoid misaligned accesses for compatibility (eg. the same code would "generally" fail on Cortex M0+ parts)
2. DMA burst across the boundary are not supported. It is quite unlikely that this will ever take place but if there is a chance you need to ensure that memory taking part in burst operations are restricted to being completely in one of the two sectors.
3. In some low leakage only one of the memory sectors may be retained. This depends on the mode and the device so consult the manual for specific details.
4. If you use bit banding on variables, only variables in the upper area can be operated on. If no bit banding on variables is used, there is no problem.



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