Problems using certain modes for Output Compare on K60 ENET_TMR

[jesperevertsson]

Hi, I've asked a similar question before: Using K60 Enet to generate and receive PPS.

I didn't get any help that time but managed to get a bit further on my own. Basically what I'm trying to accomplish is to use the Output Compare functionality of the 1588 timer in the K60 processor to generate a PPS pulse. I've managed to get it to work if I set ENET_TSCR[TMODE] to 0101 (toggle output on compare). However I want the PPS pulse to be high 200 ms and low 800 ms. I therefore set ENET_TSCR[TMODE] to 1010 (clear output on compare, set output on overflow). However, this is not working. I also tried using 10X1 which is the reversed functionality and that doesnt work either. The output compare part seem to work but not the overflow one. Yet I am still able to receive interrupts on overflow, so at least some part of the overflow functionality is working correctly.

Since TMODE 0101 is working and 1010 is not working, is there something different that is needed when configuring the registers for these two functionalities? Or is it anything else I'm missing?

Here is my code:

    PORTB_PCR2 = (0|PORT_PCR_MUX(4));

    PORTB_PCR4 = (0|PORT_PCR_MUX(4));

    ENET_TCCR0 = 0xBEBC200;

    ENET_TCSR0 = ENET_TCSR_TMODE(10);

    ENET_TCCR2 = 0x3B9AC000;

    ENET_TCSR2 = ENET_TCSR_TMODE(5);

    ENET_ATINC = 0x1414;

    SIM_SOPT2 = SIM_SOPT2_TIMESRC(2);

    ENET_ATCR |= ENET_ATCR_PEREN_MASK;

    ENET_ATCR |= ENET_ATCR_PINPER_MASK;

    ENET_ATCR |= ENET_ATCR_EN_MASK;

[mario_castaneda]

Hi Jesper,

ATCR[PINPER] is not supported on all Kinetis family, it has not effect on the pin if enabled. Also, when using Time control (TCSR, TCCR), ATCR[PEREN] is not required and not supported.

To achieve 200ms low and 800ms high:

1. Use external 50 MHz instead of internal core/system clock (which you have already done it) to get accuracy period.

2. ATPER set to 1s (0x3B9aCA00)

3. TCCRn set to 200ms (0x0BEBC200)

4. TCSRn set to mode 7 (clear) and Timer interrupt enable

5. Enable the timer

In interrupt 1588 interrupt service handler:

- Clear Timer flag

- alternating two counters (0/1) for 800ms and 200ms

- clear mode

- set desired timer to TCCRn

- set desired mode

- restart timer

example:

void fec1588_isr(void)

{

    if (ENET_TGSR & ENET_TGSR_TF2_MASK)

    {

        ENET_TCSR2 |= ENET_TCSR_TF_MASK;

        if (count == 0)

          {

            ENET_TCSR2 &= ~ENET_TCSR_TMODE_MASK;

            ENET_TCCR2 = 800000000;

            ENET_TCSR2 |= ENET_TCSR_TMODE(6);

            ENET_ATCR |= ENET_ATCR_RESTART_MASK;

            count++;

          }

          else

          {

            ENET_TCSR2 &= ~ENET_TCSR_TMODE_MASK;

            ENET_TCCR2 = 200000000;

            ENET_TCSR2 |= ENET_TCSR_TMODE(7);

            ENET_ATCR |= ENET_ATCR_RESTART_MASK;

            count = 0;

          }

    }

}

void main(void)

{

    PORTC_PCR18 = PORT_PCR_MUX(4)|PORT_PCR_PE_MASK|PORT_PCR_PS_MASK;

    SIM_SCGC2 |= 1;

    ENET_EIMR =ENET_EIMR_TS_TIMER_MASK;

    enable_irq(98 - 16);

    count = 0;

    OSC_CR |= OSC_CR_ERCLKEN_MASK;//Enable OSCERCLK

    SIM_SOPT2 = SIM_SOPT2_TIMESRC(2);

    ENET_ECR |= ENET_ECR_ETHEREN_MASK | ENET_ECR_EN1588_MASK;

    ENET_ATPER = 0x3B9ACA00;  //10^9

    ENET_ATINC = ENET_ATINC_INC(20) | ENET_ATINC_INC_CORR(20);

    ENET_TCCR2 = 200000000;

    ENET_TCSR2 = ENET_TCSR_TMODE(7) | ENET_TCSR_TIE_MASK;

    ENET_ATCR |= ENET_ATCR_EN_MASK;

}

If restart timer is not asserted, the timer will continue to run and changing the TMODE will have incorrect result from the output.

Another approach is to set ATPER to 200ms, then use the timer interrupt to toggle high or low depends on counts.

Bets Regards

Mario

[tsi-chung_liew]

Jasper,

Answering the questions from previous post:

- There is only one counter for four timers/channels (1588_TMR0-TMR3)

- Both TMODE can function at the same time when using different channel for each mode. Each channel can't have both functions.

I need more time to evaluate the issue you described above.

Regards,

TsiChung