I have a problem with configuring 32K as clock soure.. Attached is the configuration code.
MCG_C2 = 0; //new MCG_C2 = MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK; //new MCG_C1 = 0; //new /* Wait for crystal to initialize */ while (!(MCG_S & MCG_S_OSCINIT_MASK)) {}; /* Wait for Reference Clock Status bit to clear */ while (MCG_S & MCG_S_IREFST_MASK) {}; /* Wait for clock status bits to show clock source * is external reference clock */ //while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2) {}; //new while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x0) {}; //new FEE MCG_C4 |= MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(3); /* Now in FBE * Configure PLL Reference Divider, PLLCLKEN = 0, PLLSTEN = 0, PRDIV = 0x18 * The crystal frequency is used to select the PRDIV value. * Only even frequency crystals are supported * that will produce a 2MHz reference clock to the PLL. */ //MCG_C5 = MCG_C5_PRDIV(BSP_REF_CLOCK_DIV - 1); /* Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, * PLL disabled, clock monitor disabled, PLL VCO divider is clear */ MCG_C6 = 0; /* Calculate mask for System Clock Divider Register 1 SIM_CLKDIV1 */ SIM_CLKDIV1_COPY = SIM_CLKDIV1_OUTDIV1(BSP_CORE_DIV - 1) | SIM_CLKDIV1_OUTDIV2(BSP_BUS_DIV - 1) | SIM_CLKDIV1_OUTDIV3(BSP_FLEXBUS_DIV - 1) | SIM_CLKDIV1_OUTDIV4(BSP_FLASH_DIV - 1);
