PCS DSPI always active hi

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PCS DSPI always active hi

259件の閲覧回数
pietrodicastri
Senior Contributor II

Good morning

I have a remarkable behaviour for the DSPI. Using a KV58 tower .. The example from the SDK is just working normally. I can select the CS0 polarity.
I have my application using a driver SPI just as a copy paste. And the CS0 is always active hi.
I am looking over and over again ... I do not find a reason for it.
If someone wants to dedicate a little time I can send the files or the full project.
I am thankful for every support

Pietro

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250件の閲覧回数
pietrodicastri
Senior Contributor II
Hello me agan
I have a remarkable fix and question.
That's the code for the initialization of the DSPI

static bool MCP23S17_DspiInit(void)
{
dspi_master_config_t masterConfig;
uint32_t srcClock_Hz;

CLOCK_EnableClock( kCLOCK_Spi0 );
DSPI_Deinit( MCP23S17_DSPI_BASE );

DSPI_MasterGetDefaultConfig(&masterConfig);

masterConfig.whichCtar = MCP23S17_DSPI_CTAR;
masterConfig.ctarConfig.baudRate = MCP23S17_SPI_BAUDRATE;
masterConfig.ctarConfig.bitsPerFrame = MCP23S17_SPI_BITS_PER_FRAME;
masterConfig.ctarConfig.cpol = MCP23S17_SPI_CPOL;
masterConfig.ctarConfig.cpha = MCP23S17_SPI_CPHA;
masterConfig.ctarConfig.direction = MCP23S17_SPI_SHIFT_DIR;
masterConfig.ctarConfig.pcsToSckDelayInNanoSec = MCP23S17_DELAY_NS;
masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = MCP23S17_DELAY_NS;
masterConfig.ctarConfig.betweenTransferDelayInNanoSec = MCP23S17_DELAY_NS;

/* Default PCS for init; actual PCS is chosen via configFlags later */
masterConfig.whichPcs = MCP23S17_DSPI_PCS0;
masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow;

masterConfig.enableContinuousSCK = false;
masterConfig.enableRxFifoOverWrite = false;
masterConfig.enableModifiedTimingFormat = false;
masterConfig.samplePoint = kDSPI_SckToSin0Clock;

srcClock_Hz = MCP23S17_DSPI_CLK_FREQ;
if (srcClock_Hz == 0U)
{
return false;
}

DSPI_MasterInit(MCP23S17_DSPI_BASE, &masterConfig, srcClock_Hz);
SPI0->MCR |= (0x003F0000);

return true;
}


The surprise here is the line
SPI0->MCR |= (0x003F0000);

needs to be there .. After the inizialization despite the explicit setting to have a low active CS the CS is always active high. But the procedure is the same in the SDK. So
explain me what is wrong.

Thank You
Pietro
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108件の閲覧回数
Alice_Yang
NXP TechSupport
NXP TechSupport

Hello @pietrodicastri 

Please refer to the PCSIS field in the SPIx_MCR register. When a bit is set to 0, the inactive state of PCSx is low, and high indicates the active state. Also note that the effect of this bit only takes place when the module is enabled. Ensure that this bit is configured correctly before enabling the SPI interface.
Alice_Yang_0-1766472188581.png

 

BR

Alice

 

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%3CLINGO-SUB%20id%3D%22lingo-sub-2266964%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3EPCS%20DSPI%E3%81%AF%E5%B8%B8%E3%81%AB%E3%82%A2%E3%82%AF%E3%83%86%E3%82%A3%E3%83%96%E3%81%A7%E3%81%99%3C%2FLINGO-SUB%3E%3CLINGO-BODY%20id%3D%22lingo-body-2266964%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3E%3CP%3E%E3%81%8A%E3%81%AF%E3%82%88%E3%81%86%3C%2FP%3E%3CP%3E%E7%A7%81%E3%81%AF%20DSPI%20%E3%81%AB%E9%96%A2%E3%81%97%E3%81%A6%E6%B3%A8%E7%9B%AE%E3%81%99%E3%81%B9%E3%81%8D%E8%A1%8C%E5%8B%95%E3%82%92%E3%81%A8%E3%81%A3%E3%81%A6%E3%81%84%E3%81%BE%E3%81%99%E3%80%82KV58%20%E3%82%BF%E3%83%AF%E3%83%BC%E3%82%92%E4%BD%BF%E7%94%A8%E3%81%97%E3%81%A6%E3%81%84%E3%81%BE%E3%81%99%E3%80%82SDKs%20%E3%81%AE%E4%BE%8B%E3%81%AF%E6%AD%A3%E5%B8%B8%E3%81%AB%E5%8B%95%E4%BD%9C%E3%81%97%E3%81%A6%E3%81%84%E3%81%BE%E3%81%99%E3%80%82CS0%E6%A5%B5%E6%80%A7%E3%82%92%E9%81%B8%E6%8A%9E%E3%81%A7%E3%81%8D%E3%81%BE%E3%81%99%E3%80%82%3CBR%20%2F%3E%E7%A7%81%E3%81%AE%E3%82%A2%E3%83%97%E3%83%AA%E3%82%B1%E3%83%BC%E3%82%B7%E3%83%A7%E3%83%B3%E3%81%A7%E3%81%AF%E3%80%81%E3%83%89%E3%83%A9%E3%82%A4%E3%83%90%20SPI%20%E3%82%92%E3%82%B3%E3%83%94%E3%83%BC%20%E3%83%9A%E3%83%BC%E3%82%B9%E3%83%88%E3%81%97%E3%81%A6%E4%BD%BF%E7%94%A8%E3%81%97%E3%81%A6%E3%81%84%E3%81%BE%E3%81%99%E3%80%82%E3%81%9D%E3%81%97%E3%81%A6%E3%80%81CS0%20%E3%81%AF%E5%B8%B8%E3%81%AB%E3%82%A2%E3%82%AF%E3%83%86%E3%82%A3%E3%83%96%E3%81%A7%E3%81%99%E3%80%82%3CBR%20%2F%3E%E4%BD%95%E5%BA%A6%E3%82%82%E4%BD%95%E5%BA%A6%E3%82%82%E8%A6%8B%E8%BF%94%E3%81%97%E3%81%A6%E3%81%84%E3%81%BE%E3%81%99%E3%81%8C%E2%80%A6%E7%90%86%E7%94%B1%E3%81%8C%E8%A6%8B%E3%81%A4%E3%81%8B%E3%82%8A%E3%81%BE%E3%81%9B%E3%82%93%E3%80%82%3CBR%20%2F%3E%E5%B0%91%E3%81%97%E6%99%82%E9%96%93%E3%82%92%E5%89%B2%E3%81%84%E3%81%A6%E3%81%8F%E3%82%8C%E3%82%8B%E4%BA%BA%E3%81%8C%E3%81%84%E3%82%8C%E3%81%B0%E3%80%81%E3%83%95%E3%82%A1%E3%82%A4%E3%83%AB%E3%81%BE%E3%81%9F%E3%81%AF%E3%83%97%E3%83%AD%E3%82%B8%E3%82%A7%E3%82%AF%E3%83%88%E5%85%A8%E4%BD%93%E3%82%92%E9%80%81%E4%BF%A1%E3%81%A7%E3%81%8D%E3%81%BE%E3%81%99%E3%80%82%3CBR%20%2F%3E%E3%81%82%E3%82%89%E3%82%86%E3%82%8B%E3%82%B5%E3%83%9D%E3%83%BC%E3%83%88%E3%81%AB%E6%84%9F%E8%AC%9D%E3%81%97%E3%81%BE%E3%81%99%3C%2FP%3E%3CP%3E%E3%83%94%E3%82%A8%E3%83%88%E3%83%AD%3C%2FP%3E%3C%2FLINGO-BODY%3E%3CLINGO-SUB%20id%3D%22lingo-sub-2266976%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%20translate%3D%22no%22%3ERe%3A%20PCS%20DSPI%20always%20active%20hi%3C%2FLINGO-SUB%3E%3CLINGO-BODY%20id%3D%22lingo-body-2266976%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3E%E3%81%93%E3%82%93%E3%81%AB%E3%81%A1%E3%81%AF%E3%80%81%E3%81%BE%E3%81%9F%3CBR%20%2F%3E%E6%B3%A8%E7%9B%AE%E3%81%99%E3%81%B9%E3%81%8D%E4%BF%AE%E6%AD%A3%E3%81%A8%E8%B3%AA%E5%95%8F%E3%81%8C%E3%81%82%E3%82%8A%E3%81%BE%E3%81%99%E3%80%82%3CBR%20%2F%3E%E3%81%93%E3%82%8C%E3%81%AFDSPI%E3%81%AE%E5%88%9D%E6%9C%9F%E5%8C%96%E3%81%AE%E3%82%B3%E3%83%BC%E3%83%89%E3%81%A7%E3%81%99%3CBR%20%2F%3E%3CBR%20%2F%3E%E9%9D%99%E7%9A%84%E3%83%96%E3%83%BC%E3%83%ABMCP23S17_DspiInit(void)%3CBR%20%2F%3E%20%7B%3CBR%20%2F%3E%20dspi_master_config_t%20%E3%83%9E%E3%82%B9%E3%82%BF%E3%83%BC%E6%A7%8B%E6%88%90%3B%3CBR%20%2F%3E%20uint32_t%20srcClock_Hz%3B%3CBR%20%2F%3E%3CBR%20%2F%3E%20CLOCK_EnableClock(%20kCLOCK_Spi0%20)%3B%3CBR%20%2F%3E%20DSPI_Deinit(%20MCP23S17_DSPI_BASE%20)%3B%3CBR%20%2F%3E%3CBR%20%2F%3E%20DSPI_MasterGetDefaultConfig(%26amp%3BmasterConfig)%3B%3CBR%20%2F%3E%3CBR%20%2F%3E%E3%83%9E%E3%82%B9%E3%82%BF%E3%83%BCConfig.whichCtar%20%3D%20MCP23S17_DSPI_CTAR%3B%3CBR%20%2F%3E%20masterConfig.ctarConfig.baudRate%20%3D%20MCP23S17_SPI_BAUDRATE%3B%3CBR%20%2F%3E%20masterConfig.ctarConfig.bitsPerFrame%3D%20MCP23S17_SPI_BITS_PER_FRAME%3B%3CBR%20%2F%3E%E3%83%9E%E3%82%B9%E3%82%BF%E3%83%BCConfig.ctarConfig.cpol%20%3D%20MCP23S17_SPI_CPOL%3B%3CBR%20%2F%3E%E3%83%9E%E3%82%B9%E3%82%BF%E3%83%BCConfig.ctarConfig.cpha%20%3D%20MCP23S17_SPI_CPHA%3B%3CBR%20%2F%3E%20masterConfig.ctarConfig.direction%20%3D%20MCP23S17_SPI_SHIFT_DIR%3B%3CBR%20%2F%3E%E3%83%9E%E3%82%B9%E3%82%BF%E3%83%BC%E6%A7%8B%E6%88%90.ctarConfig.pcsToSckDelayInNanoSec%3D%20MCP23S17_DELAY_NS%3B%3CBR%20%2F%3E%E3%83%9E%E3%82%B9%E3%82%BF%E3%83%BC%E6%A7%8B%E6%88%90.ctarConfig.lastSckToPcsDelayInNanoSec%3D%20MCP23S17_DELAY_NS%3B%3CBR%20%2F%3E%20masterConfig.ctarConfig.betweenTransferDelayInNanoSec%3D%20MCP23S17_DELAY_NS%3B%3CBR%20%2F%3E%3CBR%20%2F%3E%20%2F*%20init%20%E3%81%AE%E3%83%87%E3%83%95%E3%82%A9%E3%83%AB%E3%83%88%20PCS%E3%80%82%E5%AE%9F%E9%9A%9B%E3%81%AE%20PCS%20%E3%81%AF%E5%BE%8C%E3%81%A7%20configFlags%20%E3%81%AB%E3%82%88%E3%81%A3%E3%81%A6%E9%81%B8%E6%8A%9E%E3%81%95%E3%82%8C%E3%81%BE%E3%81%99%20*%2F%3CBR%20%2F%3E%E3%83%9E%E3%82%B9%E3%82%BF%E3%83%BCConfig.whichPcs%20%3D%20MCP23S17_DSPI_PCS0%3B%3CBR%20%2F%3E%E3%83%9E%E3%82%B9%E3%82%BF%E3%83%BC%E6%A7%8B%E6%88%90.pcsActiveHighOrLow%3D%20kDSPI_PcsActiveLow%3B%3CBR%20%2F%3E%3CBR%20%2F%3E%E3%83%9E%E3%82%B9%E3%82%BF%E3%83%BC%E6%A7%8B%E6%88%90.enableContinuousSCK%3D%20%E5%81%BD%3B%3CBR%20%2F%3E%20masterConfig.enableRxFifoOverWrite%3D%20%E5%81%BD%3B%3CBR%20%2F%3E%20masterConfig.enableModifiedTimingFormat%3D%20%E5%8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