Martyn,
Thanks for the advice. I am shifting my irq to the left 16.
// Interrupt enabling and disabling
static inline void enable_irq(int n) {
NVIC_ICPR |= 1 << (n - 16);
NVIC_ISER |= 1 << (n - 16);
}
Do you see anything that is missing from this setup? My C1, C2, C3, C4 and S2 register seem to have the correct values. Any other ideas?
void uart1_init(int baud_rate)
{
SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;
printf("SIM_SOPT5 = %x \r\n", SIM_SOPT5);
// Turn on clock to UART1 module and select 48Mhz clock (FLL/PLL source)
SIM_SCGC4 |= SIM_SCGC4_UART1_MASK;
printf("SIM_SCGC4 = %x \r\n", SIM_SCGC4);
SIM_SOPT5 &= ~SIM_SOPT5_UART1TXSRC_MASK;
printf("SIM_SOPT5 = %x \r\n", SIM_SOPT5);
SIM_SOPT5 |= SIM_SOPT5_UART1TXSRC(0); // FLL/PLL source
printf("SIM_SOPT5 = %x \r\n", SIM_SOPT5);
// Select "Alt 3" usage to enable UART1 on pins
PORTC_PCR3 = PORT_PCR_MUX(3);
PORTC_PCR4 = PORT_PCR_MUX(3);
UART1_C2 = 0;
UART1_C1 = 0;
UART1_C3 = 0;
UART1_C4 = 0;
UART1_S2 = 0;
// Set the baud rate divisor
#define OVER_SAMPLE 16
uint16_t divisor = (CORE_CLOCK / OVER_SAMPLE) / baud_rate;
UART1_C4 = UARTLP_C4_OSR(OVER_SAMPLE - 1);
UART1_BDH = (divisor >> 8) & UARTLP_BDH_SBR_MASK;
UART1_BDL = (divisor & UARTLP_BDL_SBR_MASK);
// Enable the transmitter, receiver, and receive interrupts
UART1_C2 = UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK;
enable_irq(INT_UART1);
}
// A blocking write, useful for error/crash/debug reporting
int uart1_write_err(char *p, int len)
{
int i;
__disable_irq();
for(i=0; i<len; i++) {
while((UART1_S1 & UART_S1_TDRE_MASK) == 0); // Wait until transmit buffer empty
UART1_D = *p++; // Send char
}
__enable_irq();
return len;
}
main() {
int len = 0;
char *pyld;
pyld = (char *) malloc(39);
memset(pyld, 0, sizeof(pyld));
... build pyld ...
uart1_write_err(pyld, strlen(pyld));
}
Thanks,
Greg