NXP ICS LOC Reset

[cagri]

In a project where we use NXP MKE04Z128VQH4, we are having MCU reset problem.

When we check the SIM_SRSID register after reset, the reset cause is seen as ICS loss-of-clock (LOC). However ICS_C4[CME] is not set.

Can you help with the cause and solution of the problem?

Information about the design can be found below and in the attachment.

MCU	:	MKE04Z128VQH4
XTAL	:	AWSCR-8.00MES-C15-T
OSC_CR	:	0b10110101
ICS_C1	:	0b00011010
ICS_C2	:	0b00100000
ICS_C3	:	93
ICS_C4	:	0b00000000

[xiangjun_rong]

Hi,

I see that you connect 8MHz crystal to the XTAL/EXTAL pins for KE04.

1)I have checked your crystal connection, you do not connect the capacitors as the following Fig.

2)You set the OSC_CR[RANGE]=1, OSC_CR[HGO]=0, so you use high frequency,low power mode.

Pls try to set both the RANGE and HGO bits and have a try.

21.6.2.3 High-frequency, high-gain mode
In high-frequency, high-gain Mode (OSC_CR[RANGE] = 1, OSC_CR[HGO] = 1), the
oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail
oscillation amplitudes.

The oscillator input buffer in this mode is single-ended. It provides low pass frequency
filtering as well as hysteresis for voltage filtering and converts the output to logic levels.
21.6.2.4 High-frequency, low-power mode
In high-frequency, low-power mode (OSC_CR[RANGE] = 1, OSC_CR[HGO] = 0) the
oscillator uses a gain control loop to minimize power consumption. As the oscillation
amplitude increases, the amplifier current is reduced. This continues until a desired
amplitude is achieved at steady-state.
The oscillator input buffer in this mode is differential. It provides low pass frequency
filtering as well as hysteresis for voltage filtering and converts the output to logic levels

Hope it can help you

BR

XiangJun Rong

[cagri]

Hi,

MCU was waking up and going back to sleep every 25 seconds, so we reduced this to 2 seconds to replicate the error. At the end of the test, we saw that the processor entered a hard fault. We added while into the hard fault function and debugged it with Attach to Running Target.

After turning off the timer clock(SIM->SCGC &= ~0x2u), we saw that ISR_pit_ch1 (timer interrupt)(PIT->CHANNEL[1].TFLG |= 0x1u) came and this caused the error. Do you think LOC reset could be related to this problem?

Thank you for your support.

[xiangjun_rong]

Hi,

I do not think that hardfault error can necessarily lead to reset.

BR

XiangJun Rong