MKV46 Interrupt Delay

[tobiasoswald]

Hello NXP Community,

i'd like to ask you about a Problem i have encountered in one of my Projects.

I have set up a SPI Communication on a KV46 running at full Clock Speed. All the Bus Clocks are set to their maximum possible Speed, too. I use the CS-Signal of the SPI via a Port-Interrupt (rising Edge) to detect the End of the SPI Message, because this simplifies the whole operation a lot.

The strange thing is that there is a pretty big time delay of around 1µs between the rising edge of the CS Signal at the Pin and the moment the MCU enters the interrupt Routine.

I have checked if there are any Filters enabled on this Portpin and if the Port really is clocked at it's full speed.

I also tried to look up the maximum values for this kind of time delay, but wasn't able to find any information in the documentation provided by NXP.

I'd like to minimize this Delay, Does anybody have an Idea how i can get rid of it?

Thanks a lot!

Best Regards,

Tobias

[nxf58904]

Hi,

I get you.Before entering the ISR,the controller need to push some data likes PC and some temp data.You can debug and find how many command need to run(assembly) and if possible you can reduce some data or function ,it will get rid of it.

Jianyu: 

Have a great day,
TIC

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[nxf58904]

Hi,

According to the picture above,there has a programmable delay between assertion of the PCS signal to the first SCK edge.

It seems this cause a 1us delay.

The delay can be set from register CTAR when as a master or CTAR0 when slave.

More details get from reference manual.

Jianyu: 

Have a great day,
TIC

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[tobiasoswald]

Hi Jianyu Chen,

thaks a lot for your reply.

If i get you right, you are referring top the SPI peripheral internal delays. As far as i understand those delays, they don't come to effect in this particular case.

Although i use the Pin assigned to the PCS-Signal of the SPI, which happens to be PC5, i don't use the SPI-Internal interrupts.

I chose to use the Port-Based interrupt (PORTC_PCRN5 field IRQC = 1001), so when the SPI frame is done, PCS goes high which triggers the external Port Interrupt.

What i observe is a 1µs time delay between PCS going high and the controller entering the ISR.

Best Regards,

Tobias