MKV10Z64 - VLPS - high current draw

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MKV10Z64 - VLPS - high current draw

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chrisphelan
Contributor I

Greetings. I am using the above MCU in a device I am developing. Sleep current in VLPS is ~380uA (confirmed that this is the draw of the MCU alone). Per the datasheet, it should be much much lower. I am using the functions per SDK2.2 to enter VLPS, I am seeing a drop from run time draw (~2mA) to this sleep current draw, so I know that the MCU is entering a lower power state, but I cannot achieve the numbers I expect. All un-used pins are pulled low using internal pull downs and driven low (excluding the JTAG lines - although I suppose I could add them to the list too). Any ideas about what else I should check? Is something defaulted to on (via SDK2.2 or otherwise) that I should be disabling? I believe the core clock is disabled in VLPS so no value in dropping clock speed when sleeping, correct?

Any help is appreciated!

-Chris

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Robin_Shen
NXP TechSupport
NXP TechSupport

Test the same project and same MCU with two FRDM-KV10Z boards, get different current in VLPS.
Compare hardware of the FRDM-KV10Z, find the J12 will lead the current leakage. After cut the trace of J12 at bottom side, the current in VLPS of my FRDM-KV10Z board down to about 40μA.

Isolation UART SWD_DIO.png

Test the same project and same MCU with two FRDM-KV10Z boards but using different firmware applications for onboard OpenSDA, get different current in VLPS.
Compare firmware application of onboard OpenSDA, find different J-Link firmware will set different voltage to UART1_TX_TGTMCU_R. When use newest Board-Specific Firmwares'19_OpenSDA_FRDM-KV10Z.bin', the PTB17/UART0_TX current leakage occurs.

 

Conclusion:
We think it meet the 'Internal pull-up/down case' in Optimizing IO Power Consumption. Customer should avoid this.

Fig3_internalpullupdowncell.JPG

Best Regards,

Robin

 

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