MKL02Z32VFK4 PTB2 alternative(2) Rxd

[claeskjellstrom]

Hi, just want to know if anyone came across the same problem as I have with Rx pin PTB2.

The thing is that Txd is sending correctly at 115200b(that's verified) but when receiving it it's completely

crap but defined crap(like when the baudrate is extremely wrong). I have also verified this by connecting

a terminal prog(rxd) to listen to the message, and the message is ok at 115200b but UART is messing it up. If I send 'O','K',cr,lf the message in the rx buffer says 202(dec),106(dec),194(dec). The status flag

indicate overrun and frame error all the time. The rx is interrupted, not the tx.

Any ideas ?

Cheers

Claes

[Habib_MS]

Hello @claeskjellstrom ,

Can you give me more information about how you configured the peripheral? for example:

- 115200 baud rate

- 8 data bits

- No parity

- One stop bit

- No flow control.

For the moment, you can check an example of SDK (version 3.2) called "hello World", in this example, they use UART 0 for communicate at terminal.
BR
Habib

[claeskjellstrom]

Hi,

It turns out that FLL clock was out of tune, so funny thing was that Tx was sending correct but Rx

couldn't receive correct, I had to switch clock to MCGIRCLK instead and now it's working. I would like to know if there is any possibility to trim oscillator through Segger J-link.

/Claes

[Habib_MS · Accepted solution]

Hello again @claeskjellstrom ,

Regarding your question, I understand that you want to modify the trim register that feeds the module, through the Jlink. However, as the following post says, Jlink doesn't support this feature: https://community.nxp.com/t5/Kinetis-Design-Studio/trimming-internal-oscillator/td-p/383412.

If you need more information about the trim register, you can consult the reference manual for the chapter 21 called "Multipurpose Clock Generator (MCG)" in the register "MCG Control 3 Register (MCG_C3)" as well as "MCG Control 4 Register (MCG_C4)".

BR
Habib