Hi NXP Team
I am using Kinetis KE02 family microcontroller MKE02Z64VLD4 with external crystal oscillator 7.3728MHz as I need to generate serial port baud rate of 460800.
I have set the FLL with external crystal in FEE Engaged External Mode, with:
7.3728MHz divide by 256 = 28.8 KHz. This 28.8 KHz is fed to FLL, which then outputs
28.8 KHz * 1024 = 29.4912MHz (and BUS CLOCK at divide by 2 = 14.7456 MHz)
BUT
As per data sheet of MKE02, the FLL is optimized for 32-40 MHz output frequency range.
Input of FLL is recommended to be in the range of 31.25 KHz to 39.0625 KHz
What does it actually means?
Can I use FLL using 7.3728MHz external crystal and get a core frequency of 29.4912MHz?
Will FLL maintain the LOCK for this frequency (29.4912MHz)?
Or I cannot use the above scheme, as 28.8 KHz is lower than the recommended minimum of 31.25 KHz.
