Hi Luis
I have never used the clock configuration tool but if you have problems with setting up for the 180MHz operation here is a classic code method that does it:
MCG_C2 = (MCG_C2_FREQ_RANGE | MCG_C2_GAIN_MODE | MCG_C2_EREFS | MCG_C2_LOCRE0); // select crystal oscillator and select a suitable range
MCG_C1 = (MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_VALUE); // switch to external source (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary if the FLL will not be used)
while ((MCG_S & MCG_S_OSCINIT) == 0) {} // loop until the crystal source has been selected
while ((MCG_S & MCG_S_IREFST) != 0) {} // loop until the FLL source is no longer the internal reference clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {} // loop until the external reference clock source is valid
MCG_C5 = ((CLOCK_DIV - 1) | MCG_C5_PLLSTEN0); // now move from state FEE to state PBE (or FBE) PLL remains enabled in normal stop modes
MCG_C6 = ((CLOCK_MUL - MCG_C6_VDIV0_LOWEST) | MCG_C6_PLLS); // set the PLL multiplication factor
while ((MCG_S & MCG_S_PLLST) == 0) {} // loop until the PLLS clock source becomes valid
while ((MCG_S & MCG_S_LOCK) == 0) {} // loop until PLL locks
SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 24) | ((FLEX_CLOCK_DIVIDE - 1) << 20) | ((FLASH_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock divides
SMC_PMCTRL = SMC_PMCTRL_RUNM_HSRUN; // set high speed run mode (restrictions apply) so that the clock speeds can be obtained
MCG_C1 = (MCG_C1_CLKS_PLL_FLL | MCG_C1_FRDIV_1024); // finally move from PBE to PEE mode - switch to PLL clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL) {} // loop until the PLL clock is selected
Assuming 12MHz crystal the following are the actual values that it uses:
12MHz crystal, 180MHz core clock, 60MHz bus, 25.714285MHz flash
MCG_C2 = 0xa4;
MCG_C1 = 0x98;
while ((MCG_S & MCG_S_OSCINIT) == 0) {}
while ((MCG_S & MCG_S_IREFST) != 0) {}
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {}
MCG_C5 = 0x20;
MCG_C6 = 0x4e;
while ((MCG_S & MCG_S_PLLST) == 0) {}
while ((MCG_S & MCG_S_LOCK) == 0) {}
SIM_CLKDIV1 = 0x02260000;
SMC_PMCTRL = SMC_PMCTRL_RUNM_HSRUN;
MCG_C1 = 0x28;
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL) {}
Beware that for 180MHz core clock you must use the HSRUN mode, which means that flash programming is not possibel without first reducing clock speeds and switching to RUN mode (see the user's manual for the compete list of HSRUN mode restrictions).
Regards
Mark
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Thanks mark.
My problem was that the configuration was in RUN mode, so the frequency of the Core could not be higher than 120Mhz.
After select HSRUN, now everything is fine, I can configure the clock with Config Tool at 180 Mhz, with div at /2 and PLL at *45, for a crystal of 16Mhz.
Regards.
