MK22FX512AVMC12 hard reset issue

[Victor_Tao]

Hello NXP team,

I find a hard reset issue when I use the MK22FX512AVMC12 microcontroller:

Step1. When I use a 50us period square wave (low period=10%, high period=90%) to hard reset the MCU, MCU will most likely enter a reset status or some low-power mode and cannot jump out from this reset status. At the same times, the Reset—B level is always kept low (0.1V).

The MCU needs to be powered on and off to restored to normal. After powering on and off, Reset-B is a normal high level, and K22FX512 can work normally.

During this continuous hard reset test, sometimes JLINK failed to connect to  K22FX512. Once K22FX512 successfully connected to JLINK, the MCU flash data I read all became 0xFF. Therefore, I had to reprogram K22FX512 MCU.

Step2.When I increased the reset wave to a period of 1ms ,10ms even longer, the phenomenon in step 1 disappeared.

What I did:

1. No MCU power supply issues were found.
2. Check  the MCU specifications, the reset pulse low period should be greater than 100ns.
3. The Reset-B Pin is pulled up to 3.3V via a 4.7k resistor without a capacitance to ground. So I added a 0.1uF capacitor between the Reset-B pin and ground, forming an RC filter.  But it didn’t  work, the issue in step1 still exists.

1. The Reset Pin Control Register (RCM_RPFC) is enabled but has no effect.
2. The NMI Pin(J8) is floating. I tried to disable  the NMI function[NMI_DIS=0] ,it still doesn’t  work.

My question:

1. Is the phenomenon in step 1 normal? If not, could you share some methods to help me solve this issue?
2. Could you explain why the flash data goes to 0xFF after such hard reset?

[Celeste_Liu]

Hello @Victor_Tao ,

Thanks for your post. Can you tell me the mask set of your chip? Additionally, it would be better if you could send me your circuit diagram.

BRs,

Celeste

[Victor_Tao]

  

[Celeste_Liu]

Hello @Victor_Tao ,

Thanks for your information.

Could you let me know what is the bus clock frequency?

Accroding to RM description, Reset pin should keep low for at least 128 bus clock cycles.

And could you change the low period to 50% when using 50us period square and try it again?

BRs,

Celeste

[Victor_Tao]

Thanks to Celeste.

We use 120MHz core, Bus clock should be 60MHz or 40MHZ. I'm a little unsure.

Bus clock=40MHZ, 128 Cycles=3.2us.

Bus clock=60MHZ, 128 Cycles=2.13us.

When I use 50us period reset,10% Low=5us>>3.2us or 2.13us.

This 5us not only meet 128 bus cycles you provide, but also can meet 100ns pulse in MK22FX512 DS. But there is a hard reset issue. Can you explain it？

And I also test 50us  low period to 50% , there is no issue found this time.

[Celeste_Liu]

Hello @Victor_Tao ,

Thanks for you reply. 

The data on the datasheet is only under ideal conditions. Could you help confirm the specific value of your bus clock?

According to the RM, the Bus Clock is generated by dividing MCGOUTCLK through OUTDIV2, with a maximum frequency of 60 MHz.

How do you configure the MCG/SIM registers in your program?

Or can you measure the specific value of the bus clock through CLKOUT?

Have a nice day.

BRs,

Celeste