MK20DX256VLK7 vs. MK20DX256VLK10

[Trilliant-K20]

We have a board in production many years, using MK20DX256VLK7, no problems. Manufacturing built more boards using MK20DX256VLK10. FW boots with HardFault IRQ. I am currently tracking down with JTAG.

Question - Are DX7 & DX10 uPs interchangeable without any FW changes? Is the ONLY difference between these two uPs the Clock speed, 72MHz vs. 100MHz? Are there any register values that need to be changed for me to use DX10 (i.e. CLK registers maybe, LLWU Registers (this seems to be where hard fault occurs). Also, I am having hard time finding reference manual for these exact two uP variants. Can you please provide NXP links.

thanks,

Dan

[Trilliant-K20]

Hi Pavel, good news. I added enabling of LLWU bit 28 in SCGC4 and code is running now. Code gets farther, is running, enters Low power mode (either STOP mode or VLLS1 mode. Upon waking up due to external stimuli, seems I hit another issue. 

What may be very helpful, is there any way for NXP to provide a list of ALL Register differences between DX7 & DX10? This way we can for sure know if we are missing any other Register settings when running DX10 in code written for DX7.

thanks,

Dan

[Trilliant-K20]

More debug, if I comment out few lines dealing with configuring LLWU, then FW runs on DX10. Looking in this reference manual (which says supports : MK20DX256VMC10, not my : MK20DX256VLK10), the LLWU Registers being touched by FW seem to all match. So currently I am thinking DX7 & DX10 LLWU Registers are same. But for some reason, FW boots with DX10 uP with LLWU code not commented out.

[Pavel_Hernandez]

Hello, my name is Pavel, and I will be supporting your case, I have some questions about your project, what is the IDE that you are using? Is necessary to compile the project with the MCU target configured to avoid any unexpected issues.

Kinetis K20: 100MHz Cortex-M4 up to 512KB Flash (80pin) (nxp.com)

Kinetis K20: 72MHz Cortex-M4 up to 288KB Flash (80 pin) (nxp.com)

Best regards,
Pavel

[Trilliant-K20]

Hi Pavel, Good to hear from you. We use Eclipse IDE. Good point you make, let me verify which uP is being selected in project settings. I did not think to change uP and recompile. I verified again today, FW runs fine when using DX10 uP if I comment out any code dealing with LLWU configuration. This same FW runs fine on DX7 without commenting out LLWU related lines of code.

I will look into your question and reply back here.

thanks,

Dan

[Pavel_Hernandez]

Hello, these are the parts DN and DX with Z parts.

Spoiler

There is not enough information about the LLWU from your case but reviewed the RM about those MCUs, and maybe the hard fault is occasioned by the Clock Gate. 

Spoiler

On the RM MK20DX256VLK10 the control gate is showing.

But on the RM of MK20DX256VLK7 does not have that information.

Could you elaborate further about the LLWU? How are you set up this?

Best regards,
Pavel

[Trilliant-K20]

Spoiler

Pavel, can you explain to me the difference between MK20DX256VLK10 and MK20DX256ZVLK10? We are using MK20DX256VLK10, no "Z".

[Trilliant-K20]

So, for DX10, since our FW does not write to SIM_SCGC4 bit 28 - LLWU Clock Gate Control:
This bit controls software access to the LLWU module.
0 Access disabled
1 Access enabled

LLWU access is never enabled. This would explain why as soon as I hit first line of code which writes to any LLWU cfg register, we get HardFault ISR.

My George I think you may have found it Pavel!

[Trilliant-K20]

Here is our code. We do NOT use a MK20DZ256VLK10, even though there is a compile time -D option for it. This is from legacy code. What we DO have now is the DX7 & DX10 parts. But do note it has the SIM_SCGC4_LLWU_MASK line of code, same as you show in above Diagram for SIM SCGC4 register in RM MK20DX256VLK10.


if (defined(CPU_MK20DZ256VLK10))
/* Enable LLWU and UART3 (TTYD) Digital Clock */
SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK | \
SIM_SCGC4_UART3_MASK;
#elif (defined(CPU_MK20DX256VLK7))
/* Enable UART3 (TTYD) Digital Clock */
SIM_SCGC4 |= SIM_SCGC4_UART3_MASK;

#define SIM_SCGC4_LLWU_MASK 0x10000000u
#define SIM_SCGC4_LLWU_SHIFT 28

[Pavel_Hernandez]

Hello, I recommend using a separate project for those MCUs, that´s not the only difference the MCG in the major time is not similar, and this will not change in one line only. 

Maybe this app note could help you understand the differences, but please do not use the same project for different MCUs in your application.

nxp.com/docs/en/application-note/AN4445.pdf

Best regards,
Pavel

[Trilliant-K20]

Hi Pavel, I have been going thru AN4445.PDF. On first page, the table list part numbers and none of them = MK20DX256VLK7 vs. MK20DX256VLK10. How do we know AN4445 applies to my processors? Title of AN4445 is "Kinetis 100MHz Rev 1.x to 2.x Migration Guide".

thanks,

Dan

[Trilliant-K20]

Pavel, From App Note AN4445 you shared, is the rev 1.X of DX10 basically equivalent to DX7? Then DX10 Rev 2.X made a number of additions, changes, deletes?

"This document shows differences and describes the details of migrating from Kinetis 100 MHz Rev. 1.x to Rev. 2.x."

[Pavel_Hernandez]

Hello, I apologize if my last message was not clear, and sorry I confused the MK20DX256VLK10 with MK20DX256ZVLK10. 

I attached the app note because I think the MCU has a Z as the initial part.

Let me know more about if you separate the project.

Best regards,
Pavel

[Trilliant-K20]

Pavel,

Specifically,

1. I need to know all differences between MK20DX256VLK7 vs. MK20DX256VLK10. You pointed one out to me up above. Are there more differences between these two processors. 

2. Are there any more die revs planned for either of these two parts?

3. Can you provide list of all die revs for these two parts and any App Notes spelling out all the differences between each die rev.

If you can answer these specific three questions, that will help us to proceed.

PS - So I believe now the previous AN4445.PDF you provided is of no interest to me. because it pertains to the "Z" version of DX10. Is this correct?

thank you,

Dan

[Pavel_Hernandez]

Hello, sorry for the late response.

PS - So I believe now the previous AN4445.PDF you provided is of no interest to me. because it pertains to the "Z" version of DX10. Is this correct?
Yes, my mistake.

I recommend opening an example for the new MCU to use the configuration of the MCG and migrate the common module.

I´m afraid no app notes or documents like this.

Best regards,
Pavel

[Trilliant-K20]

I recommend opening an example for the new MCU to use the configuration of the MCG and migrate the common module.

- What examples are you referring to pavel? Can you please provide a link.

thanks,

Dan

[Pavel_Hernandez]

Hello, here you can download the SDK SDK Builder | MCUXpresso SDK Builder (nxp.com)

The MCUXpresso is built on the highly popular Eclipse platform.

Best regards,
Pavel

[Trilliant-K20]

OK Thanks, I will give it a look. Seems NXP would make things easier for developers or engineers supporting existing fielded products to determine in an easy manner differences between a code base written for DX7 vs DX10, rather than read 1400 page RM or port a new SW support package into their FW code base.

[Pavel_Hernandez]

Hello, thanks for your comments this will be taken into consideration, it would be helpful to have a migration document about this.

Best regards,
Pavel

[Trilliant-K20]

In Eclipse project properties, the Tool Settings --> Target Processor setting is only ARM family (-mpcu) = cortex-m4. I cannot locate any place where we specify uP device type.

When running Eclipse-CDT IDE debug configurations for JTAG, we use this cmd to start PE Micro JTAG GDB server - ./pegdbserver_console -device=NXP_K2x_K20DX256M7 -showflashstatus -attachonly -useexternalip -startserver

I changed to ./pegdbserver_console -device=NXP_K2x_K20DX256M10 -showflashstatus -attachonly -useexternalip -startserver,
but get same hard fault ISR when accessing LLWU config Registers on board with DX10 uP.

pegdbserver options for device type are ONLY as follows:
./pegdbserver_console -devicelist | grep NXP_K2x_K20DX256

NXP_K2x_K20DX256M7
NXP_K2x_K20DX256ZM10 (dont know what Z is here, there is an NXP DZ10 uP version, which I verified definitely has some register differences, but we are not using this uP).
NXP_K2x_K20DX256M10