I am using a KV46 in my design and have the MCG setup to run in PEE mode. I am using an external 8MHz xtal for clocking and I have the PLL setup so that the 8MHZ is /1 coming in. from there I have the vdiv set to 25 so that the PLL is clocking @200MHz feeding into the MCG clock. From the diagram in the reference manual there is no /2 block prior to running into the multiplexer of the MCGoutclk, but in the clock configurator software and indeed in the code it looks like it does get divided by 2. So the clock going into the output divider is 100MHz. For the outdiv1, outdiv2 ,and outdiv4 I have set to /1, /2, /4 respectively to get 100 MHz system clock, 50 MHz fast peripheral clock, and 25 flash memory clock. It appears to run fine with no issue. The manual excerpt from chapter 6 on clocking says, "The MCG has a PLL that provides a multiplying function on the input clock source to generate PLL clock frequencies from 110 MHz to 240 MHz and to generate PLL 2x clock frequencies from 220 MHz to 480 MHz". When I try to set the registers up through the MCUXpresso clock configurator tool to match the software driver I have, it shows errors that the PLL clock must be set between 220MHz and 480MHz. So I am wondering is my setup not correct, even though it appears to run fine and the peripheral clock that feeds SPI, CAN, & I2C seems to work correctly. Any clarity on how I should be setting the PLL up?
The 168MHz KV46 requires a PLL input between 8 .. 16 MHz; with an 8MHz crystal the input diver must be 1.
The VCO can be programmed to multiply the PLL input by 24 .. 55 (192MHz .. 440MHz from 8Mz input but to be valid the output frequency needs to be between 220MHz and 480MHz [28 .. 55 would be valid multiplications].
The PLL output is half the VCO frequency (although this is not shown in any diagrams) so valid PLL output frequencies are between 110MHz and 240MHz (MCGPLLCLK).
In RUN mode the maximum core frequency is 100MHz and in HSRUN mode it is 168MHz.
In RUN mode the lowest MCGPLLCLK is therefore too high to be used directly and thus must be divided by 2 at least.
To get 100MHz system /core frequency the PLL output must therefore be set to 200MHz (multiplier x50 to get 400MHz VCO) and the OUTDIV1 to 2. OUTDIV4 needs to be set to 8 to get the maximum bus/Flash speed of 25MHz. The fast peripheral clock can be up to 100MHz and the Nano-edge clock up to 200MHz (equal to PLL output).
Your setting of x25 for PLL multiplier may work but is operating the PLL outside of its specified range. The clock configuration tool is pointing this out and so you need to adjust (eg. to the values above) to avoid it complaining and to guarantee reliable operation.
P.S: The Tower Kit has an older KV46F150 (I don't think this is made any more) which has a different internal MCG design too, which doesn't allow 100MHz to be achieved in RUN mode from an 8MHz crystal (its multiplication range was x16..x47 and its VCO range 180MHz .. 360MHz) which only allowed 94MHz as closest legal frequency to 100MHz. I don't think there is an evaluation board with the 168MHz part so developments on the tower kit are not compatible with the 168MHz parts(!)
Configuration Tool and the Ref Manual vdiv multiplier table (dated 06/2016) only allow the the multiplier to go from 16 - x47 as you stated, is there an updated vdiv table that shows the updated values to achieve the 24- x55 multipliers, or is it assumed that the former x16 value 0x00000 is now x24 and 0x11111 is now x55? If that is the case then I am applying a x01001 which would be 264MHz divided x 2 which would have the processor running at 132MHz and the peripheral bus running at 66MHz. I didn't see a later revision RM for the KV46.
I am sorry but I made a mistake with the multiplication range - most other parts with FPU allows 24..55 and also the KV30 range do. I may have referenced an incorrect manual at the time.
16..47 is indeed the range so to get close to 100Mhz form 8MHz crystal the best that can be done is 8 x 47 = 376MHz VCO and 188MHz PLL. Divided by 2 to get 94MHz.
To get 100MHz an 8.510638MHz crystal would be needed.
No worries, just wanted to make sure I was setting the PLL up correctly,
Thanks for the information.
On Tue, Nov 20, 2018 at 11:44 AM mjbcswitzerland <email@example.com>