ADC0_CFG1 | No low power mode, divide input by 1, short sample time, single ended 12-bit conversion and bus clock. |
ADLPC = 0. No low power. ADIV = 0. Clock divided by 1. ADLSMP = 0. Short sample time. MODE = 1. 12 bits single-ended. ADICLK = 3. Bus clock as input clock (23.986 MHz). ADC0_CFG2 | Channel A selected, asynchronous clock output disabled, high speed and 2 ASDCK extra sample cycles. |
MUXSEL = 0. Channel A. ADACKEN = 0. Asynchronous clock output disabled. ADHSC = 1. High-speed. ADLSTS = 3. 2 extra ASDCK cycles, 6 in total. ADC0_SC1A | Interrupts by conversion complete enabled, single ended and ADC inactive. |
AIEN = 1. Conversion complete interrupt enabled. DIFF = 0. Single-ended conversions. CH = 31. ADC disabled (by the moment). ADC0_SC2 | Software trigger, without comparator, greater than, compare function range enabled, DMA disabled and alternate reference. |
ADTRG = 0. Software triggered. ACFE = 0. Compare function disabled. ACFGT = 1. Grater than or equal to threshold (doesn't matter because ACREN = 0). ACREN = 0. Range function disabled. DMAEN = 0. DMA disabled. REFSEL = 1. Alternate voltage reference. ADC0_SC3 | Calibration off, single conversion, average disabled. |
CAL = 0. Calibration off. ADCO = 1. Continuous conversions. AVGE = 0. Hardware average disabled. AVGS = 0. 4 samples for the hardware averaging (doesn't matter because AVGE = 0). |