KL17Z - Disabling GPIO interrupt

[dhananjayjoshi]

Hello,

We are using the KL17Z controller. The external interrupt is configured to interrupt the control on falling edge of the externally applied square wave signal. The interrupt is enabled by setting PORTA_PCR13->IRQC as 1010. There are few patches in the code which require atomic access wherein the external interrupt needs to be disabled and then enabled after executing the code patch.

eg:

func()

{

     disable_port_intr();

      ....

      ....

     enable_port_intr();

}

For doing this we are disabling the interrupt by configuring the PORTA_PCR13->IRQC as 0000. Now the problem here is, when we disable external interrupt as per above procedure it actually skips the interrupt since the controller does not even set the interrupt flag (ISF) on falling edge. As per my requirement, the control should disable the interrupt but still set the interrupt flag on falling edge and jump to the ISR after the interrupt is enabled. How to achieve this in KL17Z controller?

Thanks,

Dhananjay.

[egoodii]

You are of course correct -- modifying the IRQC field will IGNORE the 'potential interrupt condition'.  If you want to SUSPEND the handling of the interrupt, then of course you can do as the other answer and disable ALL interrupts with those "cpsid/e i" instructions (where you should be able to find macros like 'EnableInterrupts' which hide that direct-assembly from you), OR you can control the NVIC interrupt-enable for PortA (IRQ 30?) directly into the appropriate NVIC_ISER and NVIC_ICER 'set' and 'clear' enable registers using direct writes of the appropriate '1' bit [ NVIC_ICER = 1<<(INT_PORTA-16); ?].  The interrupt-event can then become 'pending' and wait for a 'set enable' to trigger.

[dhananjayjoshi]

Thanks Earl, It worked. Initially, I tried using the "|" operator for ICER eg: NVIC_ICER |= 0x40000000, but it does not work. But if we write directly without the OR logic then it works. Probably since the zeros do not change the state of other bits.

Thanks,

Dhananjay

[egoodii]

Good to hear!  I tried to make the 'direct =' requirement obvious enough --- the 'read' part of the |= read-modify-write will return ALL currently enabled interrupts, so then (as you say) the write-back to the 'clear enables' register will disable EVERYBODY.  'Ones' written to the 'clear enables' register disables the selected interrupt(s) [w1c write-one-clears function], 'ones' written to 'set enables' will enable them.

[jeremyzhou]

Hi Dhananjay,

In the FreeRTOS, it also needs to disable the interrupt before enter the critical code region and enable the interrupt again after quit the critical code region.

So I'd highly recommend the FreeRTOS's approach to make it.

func()

{ __asm volatile( "cpsid i" ); //Disable Interrupt

....

....

__asm volatile( "cpsie i" ); //Ensable Interrupt }

Have a great day,
Ping

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