Because of shortages, we're replacing the Micron MT25QL128 NOR Flash Memory with what appears to be a pin-compatible and command-compatible Cypress S25FL128S. (There are some command differences, but these commands are not used in the QSPI module).
We are using a QSPI flash Module from NXP/Freescale (attached). The commands implemented therein look like they should work without modification with the Cypress chip. Is there anything else I should watch out for?
I have similar problem . can you post the QSPI_FLASH_SetConf() code ?
Yes, I agree with you that the main difference between the two parts is the supported Instruction Codes as you mentioned. It seems that there should no other issue but please be note that finding adequate replacement is rather question for memory manufacturer. As I know memory manufacturers have typically documents describing how to transit from competitors' to their solution thus I believe they will be able to help and recommend which option is the most suitable one.
I found: Migration Guide for Micron MT25QL to Cypress S25FL-S Quad SPI Flash
One major difference is the sector layout. The Micron chip allows 4K, 32K and 64K sector operations over the entire address range, while the Cypress chip allows only 64K operations over the entire address range, and 4K sector operations only within the first 128K (or, optionally, last 128K).
The NXP/FSL QSPI demo/example does not work, even if restricted to the 4K sector range (which should work for both chips). Read ops are okay. Write and erase ops return success, but verification shows that nothing was written or erased.
I guess I'll need to get under the hood!
...actually, the verification was failing! ERASE and WRITE were working, but the READ was not.
This is because of the differing parameters for the MODE and DUMMY instructions. ('Latency Codes' also affect the choice of parameters, but I've decided to leave these at set to default, 0.)
For now only the simplest 'Fast-Read' (Single-Data-Pin and Single-Data-Rate) READ operation is successful. I have not had any success with Dual or Quad-Data-Pin, in either Single- or Double-Data-Rate, even though the sequences perfectly match the examples in section 3.2.1 of the S25FL128S datasheet.
I cannot get Quad DDR reads to work on the Cypress chip. The max read rate should be 8x: Quad DDR (4x2), but the best I can achieve is 4x: Dual DDR(2x2).
The command sequence I have for Quad DDR:
[QSPI_LUT_SEQ_DEFAULT_READ + 0] = QSPI_ENCODE_LUT_ENTRY( QSPI_ENCODE_INSTRUCTION(I_CMD, ONE_DATA_PIN, C_DDR_QUAD_IO_READ), QSPI_ENCODE_INSTRUCTION(I_ADDR_DDR, FOUR_DATA_PINS, QSPI_ADDRESS_WIDTH)), [QSPI_LUT_SEQ_DEFAULT_READ + 1] = QSPI_ENCODE_LUT_ENTRY( QSPI_ENCODE_INSTRUCTION(I_MODE_DDR, FOUR_DATA_PINS, 1), QSPI_ENCODE_INSTRUCTION(I_DUMMY, FOUR_DATA_PINS, 6)), [QSPI_LUT_SEQ_DEFAULT_READ + 2] = QSPI_ENCODE_LUT_ENTRY( QSPI_ENCODE_INSTRUCTION(I_READ_DDR, FOUR_DATA_PINS, 64), QSPI_ENCODE_INSTRUCTION(I_JMP_ON_CS, FOUR_DATA_PINS, 0)),
(See Cypress S25FL128S datasheet, page 51 for MODE and DUMMY values. Latency Code is factory default: 00)
When I read using this sequence I get 0xCCCC...CCCC instead of 0xFFFF...FFFF (virgin flash). This looks like each nibble is losing 2 bits. So data lines 0 and 1 were okay, but data lines 2 and 3 were zero. What gives?!
Okay, I have it. The default configuration for Micron chip is "Quad", while the Cypress chip is "Single/Dual". "Quad" needed to be enabled by setting Bit 1 in Configuration Register 1. Quad DDR XiP now works perfectly. I've also added functions QSPI_FLASH_GetID(), QSPI_Flash_GetConfig(), and QSPI_FLASH_SetConf() to the QSPI Flash Module source, which allow conditional setup, instead of relying on a #define or compiler switch.