K70 DDR2 controller issue

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K70 DDR2 controller issue

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lucaiser
Contributor III

Goodmorning community.

I have some problems using DDR2 controller on a kinetis K70 microcontroller. In details if i write and read 8 bit or 16 bit data, i can write a specific value in a location and read back the same value. If i do the same thing using 32bit data, i write a value but i read back a different value on same location.

Note that, if I add a delay after each write and read operation, in this case I can read back the correct value also for 32 bit data.

Controller initialization is the following:

  /* Enable DDR controller clock */

  SIM_SCGC3 |= SIM_SCGC3_DDR_MASK;

  /* Enable DDR pads and set slew rate */

  SIM_MCR |= 0xC4;   /* bits were left out of the manual so there isn't a macro right now */

  /* Software Reset */

  DDR_RCR |= DDR_RCR_RST_MASK;

  /* 10 Buffers, 150 ohm on ODT PAD CS0 */

  DDR_PAD_CTRL = 0x01000203;

 

  /* Set DRAM Class DDR2 */

  DDR_CR00 = 0x00000400;

 

  /* DDR_CR01 default on power on  :

     CSMAX = 2

     MAXCOL CR25[COLSIZ] = 11b

     MAXROW CR25[ADDPINS]  10000b - Nr of rows */

 

  DDR_CR02 = 0x02000031;

  DDR_CR03 = 0x02020506;

  DDR_CR04 = 0x06090202;

  DDR_CR05 = 0x02020302;

   

  DDR_CR06 = 0x00904002;

  DDR_CR07 = 0x01000303;

  DDR_CR08 = 0x05030201;

 

  DDR_CR09 = 0x020000c8;

 

  DDR_CR10 = 0x03003207;

  DDR_CR11 = 0x01000000;

  DDR_CR12 = 0x04920031;

  DDR_CR13 = 0x00000005;

  DDR_CR14 = 0x00C80002;

  DDR_CR15 = 0x00000032;

 

  DDR_CR16 = 0x00000001;

  /* DDR_CR17 default value */

 

  /* DDR_CR18 default value */

 

  /* DDR_CR19 default value */

 

  DDR_CR20 = 0x00030300;

 

  DDR_CR21 = 0x00040232;

 

  DDR_CR22 = 0x00000000;

 

  DDR_CR23 = 0x00040302;

 

  /* DDR_CR24 default value */

 

  DDR_CR25 = 0x0A010201;

 

  DDR_CR26 = 0x0101FFFF;

 

  DDR_CR27 = 0x01010101;

 

  DDR_CR28 = 0x00000003;

 

  DDR_CR29 = 0x00000000;

 

  DDR_CR30 = 0x00000001;

 

  DDR_CR34 = 0x02020101;

 

  /* DDR_CR35 default value */

 

  DDR_CR36 = 0x01010201;

  

  DDR_CR37 = 0x00000200;

   

  DDR_CR38 = 0x00200000;

   

  DDR_CR39 = 0x01010020;

 

  DDR_CR40 = 0x00002000;

 

  DDR_CR41 = 0x01010020;

   

  DDR_CR42 = 0x00002000;

   

  DDR_CR43 = 0x01010020;

   

  DDR_CR44 = 0x00000000;

 

  DDR_CR45 = 0x03030303;

   

  DDR_CR46 = 0x02006401;

 

  DDR_CR47 = 0x01020202;

   

  DDR_CR48 = 0x01010064;

 

  DDR_CR49 = 0x00020101;

 

  DDR_CR50 = 0x00000064;

 

  /* DDR_CR51 default value */

 

  DDR_CR52 = 0x02000602;

   

  DDR_CR53 = 0x00000000;

   

  /* DDR_CR54 default value */

 

  /* DDR_CR55 default value */

 

  DDR_CR56 = 0x02030000;

 

  DDR_CR57 = 0x01000000;

  /* DDR_CR58 default value */

  /* DDR_CR59 default value */

  /* DDR_CR60 default value */

  /* DDR_CR61 default value */

  /* DDR_CR62 default value */

  /* DDR_CR63 default value */

 

  asm("NOP");

  DDR_CR00 |= 0x00000001;

  while ((DDR_CR30 & 0x400) != 0x400)

  {

 

  }

 

  MCM_CR |= MCM_CR_DDRSIZE( 1 );   

Do you have any ideas about this behaviour?

Many thanks,

Luca

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126 Views
lucaiser
Contributor III

Hi Carlos,

we have correct our board schematic according to your suggestions but the problems was not solved. The good news is that i tried to change CAS-to-CAS delay in controller configuration and with a delay of 10 cycles i can read and write 32bit data correctly.

However i've noticed another problem when i try to write a single byte.

Consider this simple code:

#pragma location=0x09000000
static  UBYTE aubTestUsoByte[1000];

aubTestUsoByte[0] = 0xA1;

aubTestUsoByte[1] = 0xA2;

vPrintString("Value 1 = 0x");
vPrintHexChar( aubTestUsoByte[0] );
vPrintString("Value 2 = 0x");
vPrintHexChar( aubTestUsoByte[1] );

Code result is:

Value 1 = 0xA2

Value 2 = 0xA1

It seems like an inversion of values, at address 0x09000000 i find value of element 1 of my array and at address 0x09000001 i find element 0 of my array.

Do you have any idea about this behaviour?

Many thanks,

Luca Staiano

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Carlos_Musich
NXP Employee
NXP Employee

Hi Luca,

I am sorry for the delay. Can you pelase share the new schematic with the changes you did? We would like to check it first.

Regards,

Carlos

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126 Views
lucaiser
Contributor III

Hi Carlos,

thank you for your response.

I am sorry but we have not updated our schematics. However, my

colleagues of hardware department have modified one board with your

previous suggestions. If you need any information i can ask them more

details.

Consider I made a mistake. I have tried with original board and access

to memory for a single byte didn't work also all recent modifications

(hardware and software).

Let me know if you need any information.

Many thanks, bye.

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Carlos_Musich
NXP Employee
NXP Employee

Hi Luca,

I contacted the experts team. They told me that as the DDR2 is very sensitive to noise, they are not sure if just modifying board shall work fine. Using flying wire is different from implementing this directly with PCB trace on board. So they cannot say if this weird result is related to their rework.

They asked also to know which rework you have made. If you are willing to send me the reworked board, I can help check this issue.

Regards,

Carlos

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126 Views
lucaiser
Contributor III

Hi Carlos,

we have solved byte access issue. It was due to an inversion of data

mask connections.

Thank you for your support.

Best regards.

Luca Staiano

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Carlos_Musich
NXP Employee
NXP Employee

Hi Luca,

First we need to know if you are running the code on K70 tower board or you made your own board. If so, can you share schematic as well as DDR2 memory spec?

We have tried to replace the DDR init code with K70 bare-metal sample code, then run it on tower board for memory test code and did not see problem with all the three access types.

You can find such bare-metal sample code here   Kinetis 120MHz bare metal sample code

So I need more information to duplicate the issue.

Best regards,

Carlos

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Carlos_Musich
NXP Employee
NXP Employee

Hi Luca,

I am loooking at this issue with experts. Please let us know the information required above.

Regards,

Carlos

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lucaiser
Contributor III

Hi Carlos,

thank you for your reply.

I'm running code on a custom board developed by my colleagues of hardware department. I'll ask for schematic and DDR2 specs.

Did you try to replace my DDR init code on tower board?

Thanks for now.

Best regards.

Luca.

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Carlos_Musich
NXP Employee
NXP Employee

Hi Luca please see attached file with comments form our Applications Engineers.

As youare seeing problem when DDR have 32bit read/write access while it's fine for 8bit and 16bit access, this means with current circuit configuration, under high bus loading, it does not work correctly. This looks quite related to the problems in schematic. With your schematic, the voltage termination used is incorrect, and there is no differential termination on DDR_CK and DDR_CK_B, also youare using low cost solution for VREF.

You will find specific explanation on attachment.

Regards,

carlos

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lucaiser
Contributor III

Hi Carlos,

many thanks for your response. I'll fix problems in my schematic as you suggest and I'll inform you if problem is solved.

Best regards,

Luca

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126 Views
Carlos_Musich
NXP Employee
NXP Employee

Hi Luca,

were you able to get schematic and specs?

Carlos

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lucaiser
Contributor III

Hi Carlos,

i've retrieved schematic of DDR section. It's attached to this message.

We don't have a FAE assigned.

Many thanks,

Luca

Da: "Carlos_Musich" admin@community.freescale.com

A: "Luca Staiano" luca.staiano@isertech.it

Cc:

Data: Mon, 29 Feb 2016 08:59:25 -0700

Oggetto: Re: - K70 DDR2 controller issue

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K70 DDR2 controller issue

reply from Carlos_Musich in Kinetis Microcontrollers - View the full discussion

Hi Luca,>  > were you able to get schematic and specs?>  > Carlos

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Carlos_Musich
NXP Employee
NXP Employee

Thank you Luca,

I look forward for your response. Could you please also let me know if you have an FAE assigned?

Carlos

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