Hello!
We've got a TWR-K65F devel board, our custom board will be based on this later and we'll also put an SDRAM to it to satisfy our memory needs. Probably the SDRAM chip will be of different type, size, parameters etc. therefore I'm very focused on understanding all the details of SDRAM interfacing, more precisely SDRAM controller configuration.
I checked this thoroughly:
How-to-access-SDRAM-based-on-K65-SDRAM-controller/ta-p/1129000
And also generated the SDRAM sample init code by MCUXpresso for TWR85F.
The only detail I don't understand presently is the correct setting of SDRAM_CM0 register. On TWR-K65F the memory chip has 4 banks, 2048 rows and 256 columns, and the data size is 32-bits (4 * 2048 * 256 * 4 = 8MB). Because of the 32-bit data size the 2 lowest bits of address are ignored. In the MCUXpresso code and in the referred PDF the memory base address is 0x80000000.
I simply don't understand how SDRAM_CM0 value of 0x007C0001 is got. More accurately, the 14-bit wide BAM (Base Address Mask) field is ambiguous to me, and I want to be able to calculate it by myself (remember, we'll likely adapt a different SDRAM chip).
I only have one theory for calculation (frankly, I also don't believe this is right): 0x7C is binary 0111 1100. The 2 lowest bits are reserved, there 0, by "eliminating" them 11111 remains. This is decimal 31 which is quite close to the chip data size (32 bits).
Could you please someone clarify how to calculate CM0:BAM value knowing the base address (0x80000000), column width, row number, bank number, data size?
